(转)一个Altera的乘加实例

Table 1. Signed Multiply-Adder Port Listing
Port Name	Type	Description
dataa[15:0], datab[15:0], datac[15:0], datad[15:0]	Input	16-bit inputs to multiply-adder unit
result[32:0]	Output	33-bit output of multiply-adder unit

 

 

module sig_altmult_add (dataa, datab, datac, datad, result);

 input signed    [15:0] dataa;
 input signed    [15:0] datab;
 input signed    [15:0] datac;
 input signed    [15:0] datad;
 output    [32:0] result;

 wire signed    [31:0] mult0_result;
 wire signed    [31:0] mult1_result;

 assign mult0_result = dataa * datab;
 assign mult1_result = datac * datad;

 assign result = (mult0_result + mult1_result);

endmodule