a Simple Single Port RAM of Verilog Code

简单不错的单口RAM，verilog代码；

module ram32x2(clk,we,addr,data_in,data_out);

input clk,we;

input[1:0]data_in;

input[4:0]addr;

output[1:0]data_out;

reg[1:0]data_reg;

reg[1:0]mem[31:0];

reg[4:0]addrreg;

always@(clk)

begin

     if(we) mem[addr]=data_in;//=======================

     addrreg=addr;//===============================

end

assign data_out=mem[addr];

endmodule