（VHDL小程序009）用VHDL设计FDRD触发器

FDRD触发器源代码如下：

entity rdfd is

     port(

          D,RD,CE:in bit;

          CLK:in bit;

          Q:out bit

          );

end rdfd;

architecture func of rdfd is

begin

     process

     begin

     waite until clk'event and clk='1';     --clk上升沿有效

     if (CE='1' and RD='0') then           --CE/RD有效

          Q<=D;

     end if;

     end process;

end func;