(VHDL小程序005)用VHDL设计多路器
该设计为四输入多路器,当控制信号端OEbar低电平有效时,高电平有效的选择控制端R_sel,D_sel,uPC_sel,stack_sel所对应的输入数据R,D,uPC,reg_file(sp)之一送到输出Y。其中,整数sp为指向reg_file堆栈单元的指针。
源文件如下:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all; --一般不清楚用什么的情况下,这三个包都use即可。
entity multiplexer is
port(
OEbar:in std_logic;
R_sel,D_sel,uPC_sel,stack_sel:in std_logic;
sp:in integer range 0 to 5;
R,D,uPC:in std_logic_vector(11 downto 0);
Y:out std_logic_vector(11 downto 0)
);
end multiplexer;
architecture func of multiplexer is
type std_logic_array is array(5 downto 0) of std_logic_vector(11 downto 0);
begin
muxr:block-------------------------------------------------------------块block必须加标识符,不然无法通过编译;
signal temp :std_logic_vector(11 downto 0);
signal reg_file:std_logic_array:=( --需要另作定义std_logic_array
("0000 0000 0000"),
("1111 1111 1111"),
("0000 0000 0000"),
("1111 1111 1111"),
("0000 0000 0000"),
("1111 1111 1111")
);
begin
temp<=R when R_sel='1' else
D when D_sel='1' else
uPC when uPC_sel='1' else
reg_file(sp) when stack_sel='1' else
"0000 0000 0000";
Y<=temp when OEbar='0' else
"ZZZZ ZZZZ ZZZZ";
end block muxr;
end func;
===========================================
虽然temp和Y赋值是同时进行,OEbar和X_sel数据选择控制信号是同时有效,但是由于vhdl的delta延时语法现象,
可出现如下现象:
temp Y
当前 0000 0000 0000 0000 0000 0000
一个delta延迟后1111 1111 1111 0000 0000 0000
两个delta延迟后1111 1111 1111 1111 1111 1111
二维数组需要用“()”括号分开,如下:
type oooo is array(2 downto 0) of std_logic_vector(3 downto 0);
type oo is array(2 downto 0) of oooo;
signal ooooo:oo:=(
("0000","0000","0000"),
("1111","1111","1111"),
("0000","0000","0000")
);
常用数据类型定义例子如下:
--------------------------------------------
subtype abcd is integer range 0 to 555; ---integer 范围-2**31-1 to 2**31
type ddd is range 600 to 700;
--------------------------------------------
type color is (aa,b,c,d,e,f);
--------------------------------------------
type current is range 0 to 1000000000
units
na;
ua=1000na;
ma=1000ua;
a=1000ma;
end units;
---------------------------------------------
type oooo is array(2 downto 0) of std_logic_vector(3 downto 0);
type oo is array(2 downto 0) of oooo;
signal ooooo:oo:=(
("0000","0000","0000"),
("1111","1111","1111"),
("0000","0000","0000")
);
---------------------------------------------
type myrecord is record
ADDR: STD_LOCIG_VECTOR(31 DOWNTO 0);
DATA: STD_LOGIC_VECTOR(31 DOWNTO 0);
end record;
---------------------------------------------
吞风吻雨葬落日未曾彷徨 8023U1314