完整源代码：
1、head.s
.extern main
.text
.global _start
_start:
b Reset
b .
b .
b .
b .
b .
ldr pc,HandleIRQAddr
b .
HandleIRQAddr:
.long HandleIRQ
Reset:
ldr sp, =4096 @堆栈的大小不能超过4K,因为片外的SDRAM还没有初始化
@只有片内4KSRAM可用
bl disable_watch_dog
bl memsetup_2
bl init_nand
bl copy_vectors_from_nand_to_sdram
bl copy_process_from_nand_to_sdram
ldr sp, =0x30100000 @内存初始化完成，重新设置堆栈
ldr pc, =run_on_sdram @从SDRAM中继续运行
run_on_sdram:
bl mmu_tlb_init @设置页表
bl mmu_init @使能MMU
msr cpsr_c, #0xd2 @进入中断模式
ldr sp, =0x33000000 @设置中断模式堆栈
msr cpsr_c, #0xdf @进入系统模式
ldr sp, =0x30100000 @设置系统模式堆栈
bl init_irq @调用中断初始化函数
msr cpsr_c, #0x5f @设置I-bit=0，开IRQ中断
ldr lr, =halt_loop @设置返回地址
ldr pc, =main @b指令和bl指令只能前后跳转32M的范围，所以这里使用向pc赋值的方法进行跳转
halt_loop:
b halt_loop
HandleIRQ:
sub lr, lr, #4 @计算返回地址
stmdb sp!, { r0-r12,lr } @保存使用到的寄存器
ldr lr, =int_return @设置返回地址
ldr pc, =EINT_Handle @调用中断处理函数
int_return:
ldmia sp!, { r0-r12,pc }^ @中断返回, ^表示将spsr的值复制到cpsr
2、init.c
#include "s3c2440.h"
#include "init.h"
#include "mmu.h"
unsigned long const mem_cfg_val[]={ 0x22111110, //BWSCON
0x00000700, //BANKCON0
0x00000700, //BANKCON1
0x00000700, //BANKCON2
0x00000700, //BANKCON3
0x00000700, //BANKCON4
0x00000700, //BANKCON5
0x00018005, //BANKCON6
0x00018005, //BANKCON7
0x008e07a3, //REFRESH
0x000000b2, //BANKSIZE
0x00000030, //MRSRB6
0x00000030, //MRSRB7
};
void disable_watch_dog()
{
WTCON = 0;
}
void memsetup()
{
int i = 0;
unsigned long *p = (unsigned long *)MEM_CTL_BASE;
for(; i < 13; i++)
p[i] = mem_cfg_val[i];
}
void memsetup_2()
{
unsigned long *p = (unsigned long *)MEM_CTL_BASE;
p[0] = 0x22111110; //BWSCON
p[1] = 0x00000700; //BANKCON0
p[2] = 0x00000700; //BANKCON1
p[3] = 0x00000700; //BANKCON2
p[4] = 0x00000700; //BANKCON3
p[5] = 0x00000700; //BANKCON4
p[6] = 0x00000700; //BANKCON5
p[7] = 0x00018005; //BANKCON6
p[8] = 0x00018005; //BANKCON7
p[9] = 0x008e07a3; //REFRESH
p[10] = 0x000000b2; //BANKSIZE
p[11] = 0x00000030; //MRSRB6
p[12] = 0x00000030; //MRSRB7
}
void reset_nand()
{
int i=0;
NFCONF =(7<<12)|(7<<8)|(7<<4)|(0<<0);
NFCONT = (1<<4)|(0<<1)|(1<<0);
NFSTAT = 0x6;
for(; i<10; i++);
NFCMD = 0xff; //reset command
for(i=0; i<10; i++);
wait_idle();
NAND_CHIP_DISABLE;
}
void init_nand()
{
reset_nand();
}
#define BUSY 4
inline void wait_idle(void) {
int i;
while(!(NFSTAT & BUSY))
for(i=0; i<10; i++);
NFSTAT |=BUSY;
}
#define NAND_SECTOR_SIZE 512
#define NAND_BLOCK_MASK (NAND_SECTOR_SIZE - 1)
void nand_read_ll(unsigned char *buf, unsigned long start_addr, int size)
{
int i, j;
if ((start_addr & NAND_BLOCK_MASK) || (size & NAND_BLOCK_MASK)) {
return ;
}
NAND_CHIP_ENABLE;
for(i=start_addr; i < (start_addr + size);) {
NAND_CLEAR_RB;
NFCMD = 0;
NFADDR = i & 0xff;
NFADDR = (i >> 9) & 0xff;
NFADDR = (i >> 17) & 0xff;
NFADDR = (i >> 25) & 0xff;
NAND_DETECT_RB;
for(j=0; j < NAND_SECTOR_SIZE; j++, i++) {
*buf = (NFDATA & 0xff);
buf++;
}
}
NAND_CHIP_DISABLE;
return ;
}
void copy_vectors_from_nand_to_sdram()
{
nand_read_ll((unsigned char*)(VECTORS_PHY_BASE+0xf0000), 0x0, 512);
}
void copy_process_from_nand_to_sdram()
{
nand_read_ll((unsigned char*)PROCESS0_BASE, 0x0, 4096);
}
void init_irq( )
{
return;
}
3、serial.c
#include "s3c2440.h"
#include "serial.h"
#define TXD0READY (1<<2)
#define RXD0READY (1)
void init_uart( )
{//³õʼ»¯UART
GPHCON = vGPHCON;
GPHUP = vGPHUP;
UFCON0 = 0x0;
UMCON0 = 0x0;
ULCON0 = 0x3;
UCON0 = 0x245;
// UBRDIV0 = 6;
UBRDIV0 = 12;
}
void putc(unsigned char c)
{
while( ! (UTRSTAT0 & TXD0READY) );
UTXH0 = c;
}
unsigned char getc( )
{
while( ! (UTRSTAT0 & RXD0READY) );
return URXH0;
}
void printk(unsigned char* str)
{
int i = 0;
while( str[i] ){
putc( (unsigned char) str[i++] );
}
}
4、interrupt.c
#include "s3c2440.h"
#include "interrupt.h"
#include "serial.h"
void EINT_Handle()
{
printk("Interrupt occurred.\n\r");
}
5、main.c
#include "s3c2440.h"
#include "serial.h"
#define GPB5_out (1<<(5*2))
#define GPB6_out (1<<(6*2))
#define GPB7_out (1<<(7*2))
#define GPB8_out (1<<(8*2))
#define GPBCON_VA (*(volatile unsigned long *)0xb6000010)
#define GPBDAT_VA (*(volatile unsigned long *)0xb6000014)
static unsigned long m_RandSeed;
inline unsigned long Rand()
{
return (m_RandSeed=1664525L*m_RandSeed+1013904223L)>>5;
}
void wait(unsigned long dly)
{
for(; dly > 0; dly--);
}
int main()
{
unsigned long i = 0, cnt = 0;
unsigned char c;
// GPBCON = GPB5_out|GPB6_out|GPB7_out|GPB8_out;
// GPBDAT = 0;
GPBCON_VA = GPB5_out|GPB6_out|GPB7_out|GPB8_out;
GPBDAT_VA = 0;
init_uart( );
while(1){
wait(10000);
GPBDAT_VA = (~( (i++)<<5));
}
return 0;
}
6、mmu.c
[root@localhost mmu_vivi]# cat mmu.c
#include "s3c2440.h"
#include "mmu.h"
static unsigned long *mmu_tlb_base = (unsigned long *) MMU_TABLE_BASE;
void cpu_arm920_cache_clean_invalidate_all(void)
{
__asm__(
" mov r1, #0\n"
" mov r1, #7 << 5\n"
"1: orr r3, r1, #63 << 26\n"
"2: mcr p15, 0, r3, c7, c14, 2\n"
" subs r3, r3, #1 << 26\n"
" bcs 2b\n"
" subs r1, r1, #1 << 5\n"
" bcs 1b\n"
" mcr p15, 0, r1, c7, c5, 0\n"
" mcr p15, 0, r1, c7, c10, 4\n"
);
}
void cpu_arm920_tlb_invalidate_all(void)
{
__asm__(
"mov r0, #0\n"
"mcr p15, 0, r0, c7, c10, 4\n"
"mcr p15, 0, r0, c8, c7, 0\n"
);
}
void mmu_tlb_init()
{
unsigned long entry_index;
unsigned long pa;
for(entry_index = 0x30000000 ; entry_index < 0x34000000; entry_index += 0x100000){
*(mmu_tlb_base+(entry_index>>20)) = entry_index |(0x03<<10)|(0<<5)|(1<<4)|(1<<3)|0x02;
}
for(entry_index = 0x48000000; entry_index < 0x60000000; entry_index += 0x100000){
*(mmu_tlb_base+(entry_index>>20)) = entry_index |(0x03<<10)|(0<<5)|(1<<4)| 0x02;
}
pa = 0x48000000;
for(entry_index = 0xa8000000; entry_index < 0xc0000000; entry_index += 0x100000){
*(mmu_tlb_base+(entry_index>>20)) = pa |(0x03<<10)|(0<<5)|(1<<4)| 0x02;
pa += 0x100000;
}
*(mmu_tlb_base+(0xffff0000>>20)) = (VECTORS_PHY_BASE) |(0x03<<10)|(0<<5)|(1<<4)|(1<<3)|0x02;
(*(volatile unsigned long *)0x56000010) = (1<<(5*2))|(1<<(6*2))|(1<<(7*2))|(1<<(8*2));
(*(volatile unsigned long *)0x56000014) = 0x0;
cpu_arm920_cache_clean_invalidate_all();
cpu_arm920_tlb_invalidate_all();
}
void arm920_setup(void)
{
unsigned long ttb = MMU_TABLE_BASE;
__asm__(
"mov r0, #0\n"
"mcr p15, 0, r0, c7, c7, 0\n"
"mcr p15, 0, r0, c7, c10, 4\n"
"mcr p15, 0, r0, c8, c7, 0\n"
"mov r4, %0\n"
"mcr p15, 0, r4, c2, c0, 0\n"
"mvn r0, #0\n"
"mcr p15, 0, r0, c3, c0, 0\n"
"mrc p15, 0, r0, c1, c0, 0\n"
"bic r0, r0, #0x3000\n"
"bic r0, r0, #0x0300\n"
"bic r0, r0, #0x0087\n"
"orr r0, r0, #0x0002\n"
#ifdef CONFIG_CPU_D_CACHE_ON
"orr r0, r0, #0x0004\n"
#endif
#ifdef CONFIG_CPU_I_CACHE_ON
"orr r0, r0, #0x1000\n"
#endif
"orr r0, r0, #0x0001\n"
"mcr p15, 0, r0, c1, c0, 0\n"
:
: "r" (ttb) );
}
void mmu_init()
{
arm920_setup();
}
7、init.h
void disable_watch_dog();
void memsetup();
void reset_nand();
void init_nand();
inline void wait_idle(void);
void nand_read_ll(unsigned char *buf, unsigned long start_addr, int size);
void init_uart();
void copy_vectors_from_nand_to_sdram();
void copy_process_from_nand_to_sdram();
8、interrupt.h
void EINT_Handle();
9、mmu.h
#define MMU_TABLE_BASE 0x30000000
#define PROCESS0_BASE 0x30004000
#define PROCESS1_BASE 0x30100000
#define PROCESS2_BASE 0x30200000
#define VECTORS_BASE 0xffff0000
#define VECTORS_PHY_BASE 0x33f00000
void mmu_tlb_init();
void mmu_init();
10、serial.h
void putc(unsigned char c);
unsigned char getc( );
void printk(unsigned char* str);
11、s3c2440.h
[root@localhost mmu_vivi]# cat s3c2440.h
#include "hardware.h"
#include "bitfield.h"
#define USR26_MODE 0x00
#define FIQ26_MODE 0x01
#define IRQ26_MODE 0x02
#define SVC26_MODE 0x03
#define USR_MODE 0x10
#define FIQ_MODE 0x11
#define IRQ_MODE 0x12
#define SVC_MODE 0x13
#define ABT_MODE 0x17
#define UND_MODE 0x1b
#define SYSTEM_MODE 0x1f
#define MODE_MASK 0x1f
#define F_BIT 0x40
#define I_BIT 0x80
#define CC_V_BIT (1 << 28)
#define CC_C_BIT (1 << 29)
#define CC_Z_BIT (1 << 30)
#define CC_N_BIT (1 << 31)
#define R1_nF (1 << 30)
#define R1_iA (1 << 31)
#define WTCON (*(volatile unsigned long *)0x53000000)
#define MEM_CTL_BASE 0x48000000
#define bMEMCTL(Nb) __REGl(MEM_CTL_BASE + (Nb))
#define oBWSCON 0x00
#define oBANKCON0 0x04
#define oBANKCON1 0x08
#define oBANKCON2 0x0C
#define oBANKCON3 0x10
#define oBANKCON4 0x14
#define oBANKCON5 0x18
#define oBANKCON6 0x1C
#define oBANKCON7 0x20
#define oREFRESH 0x24
#define oBANKSIZE 0x28
#define oMRSRB6 0x2C
#define oMRSRB7 0x2C
#define BWSCON bMEMCTL(oBWSCON)
#define BANKCON0 bMEMCTL(oBANKCON0)
#define BANKCON1 bMEMCTL(oBANKCON1)
#define BANKCON2 bMEMCTL(oBANKCON2)
#define BANKCON3 bMEMCTL(oBANKCON3)
#define BANKCON4 bMEMCTL(oBANKCON4)
#define BANKCON5 bMEMCTL(oBANKCON5)
#define BANKCON6 bMEMCTL(oBANKCON6)
#define BANKCON7 bMEMCTL(oBANKCON7)
#define REFRESH bMEMCTL(oREFRESH)
#define BANKSIZE bMEMCTL(oBANKSIZE)
#define MRSRB6 bMEMCTL(oMRSRB6)
#define MRSRB7 bMEMCTL(oMRSRB7)
#define SELF_REFRESH (1 << 22)
#define CLK_CTL_BASE 0x4C000000
#define bCLKCTL(Nb) __REGl(CLK_CTL_BASE + (Nb))
#define oLOCKTIME 0x00
#define oMPLLCON 0x04
#define oUPLLCON 0x08
#define oCLKCON 0x0C
#define oCLKSLOW 0x10
#define oCLKDIVN 0x14
#define LOCKTIME bCLKCTL(oLOCKTIME)
#define MPLLCON bCLKCTL(oMPLLCON)
#define UPLLCON bCLKCTL(oUPLLCON)
#define CLKCON bCLKCTL(oCLKCON)
#define CLKSLOW bCLKCTL(oCLKSLOW)
#define CLKDIVN bCLKCTL(oCLKDIVN)
#define fMPLL_MDIV Fld(8,12)
#define fMPLL_PDIV Fld(6,4)
#define fMPLL_SDIV Fld(2,0)
#define GET_MDIV(x) FExtr(x, fMPLL_MDIV)
#define GET_PDIV(x) FExtr(x, fMPLL_PDIV)
#define GET_SDIV(x) FExtr(x, fMPLL_SDIV)
#define GPIO_CTL_BASE 0x56000000
#define bGPIO(p,o) __REGl(GPIO_CTL_BASE + (p) + (o))
#define oGPIO_CON 0x0
#define oGPIO_DAT 0x4
#define oGPIO_UP 0x8
#define oGPIO_RESERVED 0xC
#define oGPIO_A 0x00
#define oGPIO_B 0x10
#define oGPIO_C 0x20
#define oGPIO_D 0x30
#define oGPIO_E 0x40
#define oGPIO_F 0x50
#define oGPIO_G 0x60
#define oGPIO_H 0x70
#define oMISCCR 0x80
#define oDCLKCON 0x84
#define oEXTINT0 0x88
#define oEXTINT1 0x8C
#define oEXTINT2 0x90
#define oEINTFLT0 0x94
#define oEINTFLT1 0x98
#define oEINTFLT2 0x9C
#define oEINTFLT3 0xA0
#define oEINTMASK 0xA4
#define oEINTPEND 0xA8
#define GPACON bGPIO(oGPIO_A, oGPIO_CON)
#define GPADAT bGPIO(oGPIO_A, oGPIO_DAT)
#define GPBCON bGPIO(oGPIO_B, oGPIO_CON)
#define GPBDAT bGPIO(oGPIO_B, oGPIO_DAT)
#define GPBUP bGPIO(oGPIO_B, oGPIO_UP)
#define GPCCON bGPIO(oGPIO_C, oGPIO_CON)
#define GPCDAT bGPIO(oGPIO_C, oGPIO_DAT)
#define GPCUP bGPIO(oGPIO_C, oGPIO_UP)
#define GPDCON bGPIO(oGPIO_D, oGPIO_CON)
#define GPDDAT bGPIO(oGPIO_D, oGPIO_DAT)
#define GPDUP bGPIO(oGPIO_D, oGPIO_UP)
#define GPECON bGPIO(oGPIO_E, oGPIO_CON)
#define GPEDAT bGPIO(oGPIO_E, oGPIO_DAT)
#define GPEUP bGPIO(oGPIO_E, oGPIO_UP)
#define GPFCON bGPIO(oGPIO_F, oGPIO_CON)
#define GPFDAT bGPIO(oGPIO_F, oGPIO_DAT)
#define GPFUP bGPIO(oGPIO_F, oGPIO_UP)
#define GPGCON bGPIO(oGPIO_G, oGPIO_CON)
#define GPGDAT bGPIO(oGPIO_G, oGPIO_DAT)
#define GPGUP bGPIO(oGPIO_G, oGPIO_UP)
#define GPHCON bGPIO(oGPIO_H, oGPIO_CON)
#define GPHDAT bGPIO(oGPIO_H, oGPIO_DAT)
#define GPHUP bGPIO(oGPIO_H, oGPIO_UP)
#define MISCCR bGPIO(oMISCCR, 0)
#define DCLKCON bGPIO(oDCLKCON, 0)
#define EXTINT0 bGPIO(oEXTINT0, 0)
#define EXTINT1 bGPIO(oEXTINT1, 0)
#define EXTINT2 bGPIO(oEXTINT2, 0)
#define EINTFLT0 bGPIO(oEINTFLT0, 0)
#define EINTFLT1 bGPIO(oEINTFLT1, 0)
#define EINTFLT2 bGPIO(oEINTFLT2, 0)
#define EINTFLT3 bGPIO(oEINTFLT3, 0)
#define EINTMASK bGPIO(oEINTMASK, 0)
#define EINTPEND bGPIO(oEINTPEND, 0)
#define UART_CTL_BASE 0x50000000
#define UART0_CTL_BASE UART_CTL_BASE
#define UART1_CTL_BASE UART_CTL_BASE + 0x4000
#define UART2_CTL_BASE UART_CTL_BASE + 0x8000
#define bUART(x, Nb) __REGl(UART_CTL_BASE + (x)*0x4000 + (Nb))
#define bUARTb(x, Nb) __REGb(UART_CTL_BASE + (x)*0x4000 + (Nb))
#define oULCON 0x00
#define oUCON 0x04
#define oUFCON 0x08
#define oUMCON 0x0C
#define oUTRSTAT 0x10
#define oUERSTAT 0x14
#define oUFSTAT 0x18
#define oUMSTAT 0x1C
#define oUTXHL 0x20
#define oUTXHB 0x23
#define oURXHL 0x24
#define oURXHB 0x27
#define oUBRDIV 0x28
#define ULCON0 bUART(0, oULCON)
#define UCON0 bUART(0, oUCON)
#define UFCON0 bUART(0, oUFCON)
#define UMCON0 bUART(0, oUMCON)
#define UTRSTAT0 bUART(0, oUTRSTAT)
#define UERSTAT0 bUART(0, oUERSTAT)
#define UFSTAT0 bUART(0, oUFSTAT)
#define UMSTAT0 bUART(0, oUMSTAT)
#define UTXH0 bUARTb(0, oUTXHL)
#define URXH0 bUARTb(0, oURXHL)
#define UBRDIV0 bUART(0, oUBRDIV)
#define ULCON1 bUART(1, oULCON)
#define UCON1 bUART(1, oUCON)
#define UFCON1 bUART(1, oUFCON)
#define UMCON1 bUART(1, oUMCON)
#define UTRSTAT1 bUART(1, oUTRSTAT)
#define UERSTAT1 bUART(1, oUERSTAT)
#define UFSTAT1 bUART(1, oUFSTAT)
#define UMSTAT1 bUART(1, oUMSTAT)
#define UTXH1 bUARTb(1, oUTXHL)
#define URXH1 bUARTb(1, oURXHL)
#define UBRDIV1 bUART(1, oUBRDIV)
#define ULCON2 bUART(2, oULCON)
#define UCON2 bUART(2, oUCON)
#define UFCON2 bUART(2, oUFCON)
#define UMCON2 bUART(2, oUMCON)
#define UTRSTAT2 bUART(2, oUTRSTAT)
#define UERSTAT2 bUART(2, oUERSTAT)
#define UFSTAT2 bUART(2, oUFSTAT)
#define UMSTAT2 bUART(2, oUMSTAT)
#define UTXH2 bUARTb(2, oUTXHL)
#define URXH2 bUARTb(2, oURXHL)
#define UBRDIV2 bUART(2, oUBRDIV)
#define UTRSTAT_TX_EMPTY (1 << 2)
#define UTRSTAT_RX_READY (1 << 0)
#define UART_ERR_MASK 0xF
#define vGPHCON 0x0016faaa
#define vGPHUP 0x000007ff
#define INT_CTL_BASE 0x4A000000
#define bINT_CTL(Nb) __REG(INT_CTL_BASE + (Nb))
#define oSRCPND 0x00
#define oINTMOD 0x04
#define oINTMSK 0x08
#define oPRIORITY 0x0a
#define oINTPND 0x10
#define oINTOFFSET 0x14
#define oSUBSRCPND 0x18
#define oINTSUBMSK 0x1C
#define SRCPND bINT_CTL(oSRCPND)
#define INTMOD bINT_CTL(oINTMOD)
#define INTMSK bINT_CTL(oINTMSK)
#define PRIORITY bINT_CTL(oPRIORITY)
#define INTPND bINT_CTL(oINTPND)
#define INTOFFSET bINT_CTL(oINTOFFSET)
#define SUBSRCPND bINT_CTL(oSUBSRCPND)
#define INTSUBMSK bINT_CTL(oINTSUBMSK)
#define INT_ADCTC (1 << 31)
#define INT_RTC (1 << 30)
#define INT_SPI1 (1 << 29)
#define INT_UART0 (1 << 28)
#define INT_IIC (1 << 27)
#define INT_USBH (1 << 26)
#define INT_USBD (1 << 25)
#define INT_RESERVED24 (1 << 24)
#define INT_UART1 (1 << 23)
#define INT_SPI0 (1 << 22)
#define INT_MMC (1 << 21)
#define INT_DMA3 (1 << 20)
#define INT_DMA2 (1 << 19)
#define INT_DMA1 (1 << 18)
#define INT_DMA0 (1 << 17)
#define INT_LCD (1 << 16)
#define INT_UART2 (1 << 15)
#define INT_TIMER4 (1 << 14)
#define INT_TIMER3 (1 << 13)
#define INT_TIMER2 (1 << 12)
#define INT_TIMER1 (1 << 11)
#define INT_TIMER0 (1 << 10)
#define INT_WDT (1 << 9)
#define INT_TICK (1 << 8)
#define INT_BAT_FLT (1 << 7)
#define INT_RESERVED6 (1 << 6)
#define INT_EINT8_23 (1 << 5)
#define INT_EINT4_7 (1 << 4)
#define INT_EINT3 (1 << 3)
#define INT_EINT2 (1 << 2)
#define INT_EINT1 (1 << 1)
#define INT_EINT0 (1 << 0)
#define INT_ADC (1 << 10)
#define INT_TC (1 << 9)
#define INT_ERR2 (1 << 8)
#define INT_TXD2 (1 << 7)
#define INT_RXD2 (1 << 6)
#define INT_ERR1 (1 << 5)
#define INT_TXD1 (1 << 4)
#define INT_RXD1 (1 << 3)
#define INT_ERR0 (1 << 2)
#define INT_TXD0 (1 << 1)
#define INT_RXD0 (1 << 0)
#define NAND_CTL_BASE 0x4E000000
#define bINT_CTL(Nb) __REG(INT_CTL_BASE + (Nb))
#define oNFCONF 0x00
#define oNFCONT 0x04
#define oNFCMD 0x08
#define oNFADDR 0x0c
#define oNFDATA 0x10
#define oNFSTAT 0x20
#define oNFECC 0x2c
#define bPWM_TIMER(Nb) __REG(0x51000000 + (Nb))
#define bPWM_BUFn(Nb,x) bPWM_TIMER(0x0c + (Nb)*0x0c + (x))
#define TCFG0 bPWM_TIMER(0x00)
#define TCFG1 bPWM_TIMER(0x04)
#define TCON bPWM_TIMER(0x08)
#define TCNTB0 bPWM_BUFn(0,0x0)
#define TCMPB0 bPWM_BUFn(0,0x4)
#define TCNTO0 bPWM_BUFn(0,0x8)
#define TCNTB1 bPWM_BUFn(1,0x0)
#define TCMPB1 bPWM_BUFn(1,0x4)
#define TCNTO1 bPWM_BUFn(1,0x8)
#define TCNTB2 bPWM_BUFn(2,0x0)
#define TCMPB2 bPWM_BUFn(2,0x4)
#define TCNTO2 bPWM_BUFn(2,0x8)
#define TCNTB3 bPWM_BUFn(3,0x0)
#define TCMPB3 bPWM_BUFn(3,0x4)
#define TCNTO3 bPWM_BUFn(3,0x8)
#define TCNTB4 bPWM_BUFn(4,0x0)
#define TCNTO4 bPWM_BUFn(4,0x4)
#define fTCFG0_DZONE Fld(8,16)
#define fTCFG0_PRE1 Fld(8,8)
#define fTCFG0_PRE0 Fld(8,0)
#define fTCFG1_MUX4 Fld(4,16)
#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE)
#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1)
#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0)
#define TCON_4_AUTO (1 << 22)
#define TCON_4_UPDATE (1 << 21)
#define TCON_4_ONOFF (1 << 20)
#define COUNT_4_ON (TCON_4_ONOFF*1)
#define COUNT_4_OFF (TCON_4_ONOFF*0)
#define TCON_3_AUTO (1 << 19)
#define TIMER3_ATLOAD_ON (TCON_3_AUTO*1)
#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO)
#define TCON_3_INVERT (1 << 18)
#define TIMER3_IVT_ON (TCON_3_INVERT*1)
#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT))
#define TCON_3_MAN (1 << 17)
#define TIMER3_MANUP (TCON_3_MAN*1)
#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN))
#define TCON_3_ONOFF (1 << 16)
#define TIMER3_ON (TCON_3_ONOFF*1)
#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF))
#define GET_PRESCALE_TIMER4(x) FExtr((x), fTCFG0_PRE1)
#define GET_DIVIDER_TIMER4(x) FExtr((x), fTCFG1_MUX4)
#define bNAND_CTL(Nb) __REG(0x4e000000 + (Nb))
#define NFCONF bNAND_CTL(0x00)
#define NFCONT bNAND_CTL(0x04)
#define NFCMD bNAND_CTL(0x08)
#define NFADDR bNAND_CTL(0x0c)
#define NFDATA __REGb(0x4e000000 + (0x10))
#define NFSTAT bNAND_CTL(0x20)
#define NFECC bNAND_CTL(0x2c)
#define fNFCONF_TWRPH1 Fld(3,4)
#define NFCONF_TWRPH1 FMsk(fNFCONF_TWRPH1)
#define NFCONF_TWRPH1_7 FInsrt(0x7, fNFCONF_TWRPH1)
#define fNFCONF_TWRPH0 Fld(3,8)
#define NFCONF_TWRPH0 FMsk(fNFCONF_TWRPH0)
#define NFCONF_TWRPH0_7 FInsrt(0x7, fNFCONF_TWRPH0)
#define fNFCONF_TACLS Fld(3,12)
#define NFCONF_TACLS FMsk(fNFCONF_TACLS)
#define NFCONF_TACLS_7 FInsrt(0x7, fNFCONF_TACLS)
#define fNFCONT_nFCE Fld(1,1)
#define NFCONT_nFCE FMsk(fNFCONT_nFCE)
#define NFCONT_nFCE_LOW FInsrt(0x0, fNFCONT_nFCE)
#define NFCONT_nFCE_HIGH FInsrt(0x1, fNFCONT_nFCE)
#define fNFCONT_ECC Fld(1,4)
#define NFCONT_ECC FMsk(fNFCONT_ECC)
#define NFCONT_ECC_NINIT FInsrt(0x0, fNFCONT_ECC)
#define NFCONT_ECC_INIT FInsrt(0x1, fNFCONT_ECC)
#define fNFCONT_MAINECC Fld(1,5)
#define NFCONT_MAINECC FMsk(fNFCONT_MAINECC)
#define NFCONT_MAINECC_UNLOCK FInsrt(0x0, fNFCONT_MAINECC)
#define NFCONT_MAINECC_LOCK FInsrt(0x1, fNFCONT_MAINECC)
#define fNFCONF_ADDRSTEP Fld(1,13)
#define NFCONF_ADDRSTEP FMsk(fNFCONF_ADDRSTEP)
#define fNFCONF_PAGESIZE Fld(1,2)
#define NFCONF_PAGESIZE FMsk(fNFCONF_PAGESIZE)
#define NFCONF_PAGESIZE_256 FInsrt(0x0, fNFCONF_PAGESIZE)
#define NFCONF_PAGESIZE_512 FInsrt(0x1, fNFCONF_PAGESIZE)
#define fNFCONT_FCTRL Fld(1,0)
#define NFCONT_FCTRL FMsk(fNFCONT_FCTRL)
#define NFCONT_FCTRL_DIS FInsrt(0x0, fNFCONT_FCTRL)
#define NFCONT_FCTRL_EN FInsrt(0x1, fNFCONT_FCTRL)
#define NFSTAT_RnB (1 << 2)
#define NAND_CHIP_ENABLE (NFCONT &= ~(1<<1))
#define NAND_CHIP_DISABLE (NFCONT |= (1<<1))
#define NAND_CLEAR_RB (NFSTAT |= (1<<2))
#define NAND_DETECT_RB { while(! (NFSTAT&(1<<2)) );}
#define SPI_CLK (1 << 18)
#define IIS_CLK (1 << 17)
#define IIC_CLK (1 << 16
#define ADC_CLK (1 << 15)
#define RTC_CLK (1 << 14)
#define GPIO_CLK (1 << 13)
#define UART2_CLK (1 << 12)
#define UART1_CLK (1 << 11)
#define UART0_CLK (1 << 10)
#define SDI_CLK (1 << 9)
#define PWM_CLK (1 << 8)
#define USBSLAVE_CLK (1 << 7)
#define USBHOST_CLK (1 << 6)
#define LCDC_CLK (1 << 5)
#define NANDCTL_CLK (1 << 4)
#define SLEEP_ON (1 << 3)
#define IDLE (1 << 2)
#define GSTATUS(Nb) __REG(0x560000AC + (Nb*4))
#define GSTATUS0 GSTATUS(0)
#define GSTATUS1 GSTATUS(1)
#define GSTATUS2 GSTATUS(2)
#define GSTATUS3 GSTATUS(3)
#define GSTATUS4 GSTATUS(4)
#define PMST GSTATUS2
#define PMSR0 GSTATUS3
#define PMSR1 GSTATUS4
#define PMCTL0 CLKCON
#define PMCTL1 MISCCR
#define SCLKE (1 << 19)
#define SCLK1 (1 << 18)
#define SCLK0 (1 << 17)
#define USBSPD1 (1 << 13)
#define USBSPD0 (1 << 12)
#define PMST_HWR (1 << 0)
#define PMST_SMR (1 << 1)
#define PMST_WDR (1 << 2)
#define HIDDEN(Nb) __REG(0x560000C0 + (Nb*4))
#define FLTOUT HIDDEN(0)
#define DSC0 HIDDEN(1)
#define DSC1 HIDDEN(2)
#define MSLCON HIDDEN(3)
13、bitfield.h
#ifndef __BITFIELD_H
#define __BITFIELD_H
#ifndef __ASSEMBLY__
#define UData(Data) ((unsigned long) (Data))
#else
#define UData(Data) (Data)
#endif
#define Fld(Size, Shft) (((Size) << 16) + (Shft))
#define FSize(Field) ((Field) >> 16)
#define FShft(Field) ((Field) & 0x0000FFFF)
#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
#define F1stBit(Field) (UData (1) << FShft (Field))
#define FInsrt(Value, Field) \
(UData (Value) << FShft (Field))
#define FExtr(Data, Field) \
((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
#endif
14、hardware.h
#ifndef _HARDWARE_H_
#define _HARDWARE_H_
#define CTL_REG_READ(addr) (*(volatile unsigned long *)(addr))
#define CTL_REG_WRITE(addr, val) (*(volatile unsigned long *)(addr) = (val))
#define CTL_REG_READ_BYTE(addr) (*(volatile unsigned char *)(addr))
#define CTL_REG_WRITE_BYTE(addr, val) (*(volatile unsigned char *)(addr) = (val))
#ifndef __ASSEMBLY__
#define __REG(x) (*(volatile unsigned long *)(x))
#define __REGl(x) (*(volatile unsigned long *)(x))
#define __REGw(x) (*(volatile unsigned short *)(x))
#define __REGb(x) (*(volatile unsigned char *)(x))
#else
#define __REG(x) (x)
#define __REGl(x) (x)
#define __REGw(x) (x)
#define __REGb(x) (x)
#endif
#endif
15、mmu.lds
SECTIONS {
. = 0x30004000;
.init : AT(0){
head.o
*.o
}
}
16、Makefile
mmu : head.s main.c init.c init.h mmu.c mmu.h s3c2440.h serial.h interrupt.c interrupt.h
arm-linux-gcc -c -o head.o head.s
arm-linux-gcc -c -o init.o init.c
arm-linux-gcc -c -o serial.o serial.c
arm-linux-gcc -c -o mmu.o mmu.c
arm-linux-gcc -c -o interrupt.o interrupt.c
arm-linux-gcc -c -o main.o main.c
arm-linux-ld -Tmmu.lds head.o init.o main.o serial.o interrupt.o mmu.o -o mmu_tmp.o
arm-linux-objcopy -O binary -S mmu_tmp.o mmu
arm-linux-objdump -D -b binary -m arm mmu
arm-linux-nm -n -a mmu_tmp.o > mmu_sys.map
clean:
rm -f head.o init.o main.o mmu.o tmp.o serial.o mmu_tmp.o interrupt.o mmu mmu_sys.map
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