verilog中的初值问题

这是修改后的一段代码，黄色部分是后加的，用modelsim仿真时，若不加这一段，则Cont初始值为“XXX...XXX”即为高阻，而用Quartus II自带的仿真器仿真时，Cont初始值为0。

 1 module Count(CLOCK_50, LED, KEY);
 2 output [7:0] LED;
 3 input CLOCK_50;
 4 input KEY ;
 5 
 6 reg [22:0] Cont;
 7 reg [7:0] mLED;
 8 reg [7:0] number;
 9 
10 always@(posedge CLOCK_50) 
11 begin
12 if(!KEY)
13 Cont<=22'd0;
14 else
15 Cont <= Cont+1'b1;
16 end
17 
18 always @ (posedge Cont[2] or negedge KEY)
19 begin
20 if (!KEY)
21 begin 
22 mLED = 8'b00000000;
23 number = 0;
24 end
25 else
26 case (number)
27 0: begin mLED = 8'b00000000; number = 1;end
28 1: begin mLED = 8'b00000001; number = 2;end
29 2: begin mLED = 8'b00000011; number = 3;end
30 3: begin mLED = 8'b00000111; number = 4;end
31 4: begin mLED = 8'b00001111; number = 5;end
32 5: begin mLED = 8'b00011111; number = 6;end
33 6: begin mLED = 8'b00111111; number = 7;end
34 7: begin mLED = 8'b01111111; number = 8;end
35 8: begin mLED = 8'b11111111; number = 9;end
36 9: begin mLED = 8'b11111110; number = 10;end
37 10: begin mLED = 8'b11111100; number = 11;end
38 11: begin mLED = 8'b11111000; number = 12;end
39 12: begin mLED = 8'b11110000; number = 13;end
40 13: begin mLED = 8'b11100000; number = 14;end
41 14: begin mLED = 8'b11000000; number = 15;end
42 15: begin mLED = 8'b10000000; number = 16;end
43 16: begin mLED = 8'b00000000; number = 17;end
44 17: begin mLED = 8'b10000000; number = 18;end
45 18: begin mLED = 8'b11000000; number = 19;end
46 19: begin mLED = 8'b11100000; number = 20;end
47 20: begin mLED = 8'b11110000; number = 21;end
48 21: begin mLED = 8'b11111000; number = 22;end
49 22: begin mLED = 8'b11111100; number = 23;end
50 23: begin mLED = 8'b11111110; number = 24;end
51 24: begin mLED = 8'b11111111; number = 25;end
52 25: begin mLED = 8'b01111111; number = 26;end
53 26: begin mLED = 8'b00111111; number = 27;end
54 27: begin mLED = 8'b00011111; number = 28;end
55 28: begin mLED = 8'b00001111; number = 29;end
56 29: begin mLED = 8'b00000111; number = 30;end
57 30: begin mLED = 8'b00000011; number = 31;end
58 31: begin mLED = 8'b00000001; number = 0;end
59 default: begin mLED = 8'b00000000; number = 1;end
60 endcase
61 end
62 
63 assign LED = ~mLED;
64 
65 endmodule



posted on 2012-03-30 15:51  Xilinx&Altera  阅读(503)  评论(0)    收藏  举报

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