组合逻辑中大位宽数据时序约束问题研究

[干货]FPGA设计中大位宽、高时钟频率时序问题调试经验总结-腾讯云开发者社区-腾讯云 (tencent.com)

0.写入FIFO前多打两拍可以很好的解决问题；

1.组合逻辑的条件判别不适合使用大尾款数据，但是转换成时序小位宽信号可以很好的解决这些问题；

（下面是一个修改后的例子，这为我节省了300的TNS）

    always @(posedge I_clk) begin
        if(sync_rst_n == 1'b0) begin
            state_ch0_flag <= 1'b0;
        end else if(state == state_ch0_1 && I_ch0_end == 1'b1) begin
            state_ch0_flag <= 1'b0; 
        end else if(state == state_aribe &&  step[2] == 1'b1 && step[3] == 1'b0 && S3_req_Concat == 4'b0001) begin
            state_ch0_flag <= 1'b1;
        end
    end

    always @(posedge I_clk) begin
        if(sync_rst_n == 1'b0) begin
            state_ch1_flag <= 1'b0;
        end else if(state == state_ch1_1 && I_ch1_end == 1'b1) begin
            state_ch1_flag <= 1'b0; 
        end else if(state == state_aribe &&  step[2] == 1'b1 && step[3] == 1'b0 && S3_req_Concat == 4'b0010) begin
            state_ch1_flag <= 1'b1;
        end
    end

    always @(posedge I_clk) begin
        if(sync_rst_n == 1'b0) begin
            state_ch2_flag <= 1'b0;
        end else if(state == state_ch2_1 && I_ch2_end == 1'b1) begin
            state_ch2_flag <= 1'b0; 
        end else if(state == state_aribe &&  step[2] == 1'b1 && step[3] == 1'b0 && S3_req_Concat == 4'b0100) begin
            state_ch2_flag <= 1'b1;
        end
    end

    always @(posedge I_clk) begin
        if(sync_rst_n == 1'b0) begin
            state_ch3_flag <= 1'b0;
        end else if(state == state_ch3_1 && I_ch3_end == 1'b1) begin
            state_ch3_flag <= 1'b0; 
        end else if(state == state_aribe &&  step[2] == 1'b1 && step[3] == 1'b0 && S3_req_Concat == 4'b1000) begin
            state_ch3_flag <= 1'b1;
        end
    end

    always @(*) begin
        if(state_ch0_flag == 1'b1) begin
            M_AXI_AWID        <= CH0_M_AXI_AWID   ;
            M_AXI_AWADDR      <= CH0_M_AXI_AWADDR ;
            M_AXI_AWLEN       <= CH0_M_AXI_AWLEN  ;
            M_AXI_AWSIZE      <= CH0_M_AXI_AWSIZE ;
            M_AXI_AWBURST     <= CH0_M_AXI_AWBURST;
            M_AXI_AWLOCK      <= CH0_M_AXI_AWLOCK ;
            M_AXI_AWCACHE     <= CH0_M_AXI_AWCACHE;
            M_AXI_AWPROT      <= CH0_M_AXI_AWPROT ;
            M_AXI_AWQOS       <= CH0_M_AXI_AWQOS  ;
            M_AXI_AWUSER      <= CH0_M_AXI_AWUSER ;
            M_AXI_AWVALID     <= CH0_M_AXI_AWVALID;
            CH0_M_AXI_AWREADY <= M_AXI_AWREADY    ;
            M_AXI_WDATA       <= CH0_M_AXI_WDATA  ;
            M_AXI_WSTRB       <= CH0_M_AXI_WSTRB  ;
            M_AXI_WLAST       <= CH0_M_AXI_WLAST  ;
            M_AXI_WUSER       <= CH0_M_AXI_WUSER  ;
            M_AXI_WVALID      <= CH0_M_AXI_WVALID ;
            CH0_M_AXI_WREADY  <= M_AXI_WREADY     ;
            CH0_M_AXI_BID     <= M_AXI_BID        ;
            CH0_M_AXI_BRESP   <= M_AXI_BRESP      ;
            CH0_M_AXI_BUSER   <= M_AXI_BUSER      ;
            CH0_M_AXI_BVALID  <= M_AXI_BVALID     ;
            M_AXI_BREADY      <= CH0_M_AXI_BREADY ;
        end else if(state_ch1_flag == 1'b1) begin
            M_AXI_AWID        <= CH1_M_AXI_AWID   ;
            M_AXI_AWADDR      <= CH1_M_AXI_AWADDR ;
            M_AXI_AWLEN       <= CH1_M_AXI_AWLEN  ;
            M_AXI_AWSIZE      <= CH1_M_AXI_AWSIZE ;
            M_AXI_AWBURST     <= CH1_M_AXI_AWBURST;
            M_AXI_AWLOCK      <= CH1_M_AXI_AWLOCK ;
            M_AXI_AWCACHE     <= CH1_M_AXI_AWCACHE;
            M_AXI_AWPROT      <= CH1_M_AXI_AWPROT ;
            M_AXI_AWQOS       <= CH1_M_AXI_AWQOS  ;
            M_AXI_AWUSER      <= CH1_M_AXI_AWUSER ;
            M_AXI_AWVALID     <= CH1_M_AXI_AWVALID;
            CH1_M_AXI_AWREADY <= M_AXI_AWREADY    ;
            M_AXI_WDATA       <= CH1_M_AXI_WDATA  ;
            M_AXI_WSTRB       <= CH1_M_AXI_WSTRB  ;
            M_AXI_WLAST       <= CH1_M_AXI_WLAST  ;
            M_AXI_WUSER       <= CH1_M_AXI_WUSER  ;
            M_AXI_WVALID      <= CH1_M_AXI_WVALID ;
            CH1_M_AXI_WREADY  <= M_AXI_WREADY     ;
            CH1_M_AXI_BID     <= M_AXI_BID        ;
            CH1_M_AXI_BRESP   <= M_AXI_BRESP      ;
            CH1_M_AXI_BUSER   <= M_AXI_BUSER      ;
            CH1_M_AXI_BVALID  <= M_AXI_BVALID     ;
            M_AXI_BREADY      <= CH1_M_AXI_BREADY ;
        end else if(state_ch2_flag == 1'b1) begin
            M_AXI_AWID        <= CH2_M_AXI_AWID   ;
            M_AXI_AWADDR      <= CH2_M_AXI_AWADDR ;
            M_AXI_AWLEN       <= CH2_M_AXI_AWLEN  ;
            M_AXI_AWSIZE      <= CH2_M_AXI_AWSIZE ;
            M_AXI_AWBURST     <= CH2_M_AXI_AWBURST;
            M_AXI_AWLOCK      <= CH2_M_AXI_AWLOCK ;
            M_AXI_AWCACHE     <= CH2_M_AXI_AWCACHE;
            M_AXI_AWPROT      <= CH2_M_AXI_AWPROT ;
            M_AXI_AWQOS       <= CH2_M_AXI_AWQOS  ;
            M_AXI_AWUSER      <= CH2_M_AXI_AWUSER ;
            M_AXI_AWVALID     <= CH2_M_AXI_AWVALID;
            CH2_M_AXI_AWREADY <= M_AXI_AWREADY    ;
            M_AXI_WDATA       <= CH2_M_AXI_WDATA  ;
            M_AXI_WSTRB       <= CH2_M_AXI_WSTRB  ;
            M_AXI_WLAST       <= CH2_M_AXI_WLAST  ;
            M_AXI_WUSER       <= CH2_M_AXI_WUSER  ;
            M_AXI_WVALID      <= CH2_M_AXI_WVALID ;
            CH2_M_AXI_WREADY  <= M_AXI_WREADY     ;
            CH2_M_AXI_BID     <= M_AXI_BID        ;
            CH2_M_AXI_BRESP   <= M_AXI_BRESP      ;
            CH2_M_AXI_BUSER   <= M_AXI_BUSER      ;
            CH2_M_AXI_BVALID  <= M_AXI_BVALID     ;
            M_AXI_BREADY      <= CH2_M_AXI_BREADY ;
        end else if(state_ch3_flag == 1'b1) begin
            M_AXI_AWID        <= CH3_M_AXI_AWID   ; 
            M_AXI_AWADDR      <= CH3_M_AXI_AWADDR ;
            M_AXI_AWLEN       <= CH3_M_AXI_AWLEN  ;
            M_AXI_AWSIZE      <= CH3_M_AXI_AWSIZE ;
            M_AXI_AWBURST     <= CH3_M_AXI_AWBURST;
            M_AXI_AWLOCK      <= CH3_M_AXI_AWLOCK ;
            M_AXI_AWCACHE     <= CH3_M_AXI_AWCACHE;
            M_AXI_AWPROT      <= CH3_M_AXI_AWPROT ;
            M_AXI_AWQOS       <= CH3_M_AXI_AWQOS  ;
            M_AXI_AWUSER      <= CH3_M_AXI_AWUSER ;
            M_AXI_AWVALID     <= CH3_M_AXI_AWVALID;
            CH3_M_AXI_AWREADY <= M_AXI_AWREADY    ;
            M_AXI_WDATA       <= CH3_M_AXI_WDATA  ;
            M_AXI_WSTRB       <= CH3_M_AXI_WSTRB  ;
            M_AXI_WLAST       <= CH3_M_AXI_WLAST  ;
            M_AXI_WUSER       <= CH3_M_AXI_WUSER  ;
            M_AXI_WVALID      <= CH3_M_AXI_WVALID ;
            CH3_M_AXI_WREADY  <= M_AXI_WREADY     ;
            CH3_M_AXI_BID     <= M_AXI_BID        ;
            CH3_M_AXI_BRESP   <= M_AXI_BRESP      ;
            CH3_M_AXI_BUSER   <= M_AXI_BUSER      ;
            CH3_M_AXI_BVALID  <= M_AXI_BVALID     ;
            M_AXI_BREADY      <= CH3_M_AXI_BREADY ;
        end else begin
            M_AXI_AWID        <= CH3_M_AXI_AWID   ;
            M_AXI_AWADDR      <= CH3_M_AXI_AWADDR ;
            M_AXI_AWLEN       <= CH3_M_AXI_AWLEN  ;
            M_AXI_AWSIZE      <= CH3_M_AXI_AWSIZE ;
            M_AXI_AWBURST     <= CH3_M_AXI_AWBURST;
            M_AXI_AWLOCK      <= CH3_M_AXI_AWLOCK ;
            M_AXI_AWCACHE     <= CH3_M_AXI_AWCACHE;
            M_AXI_AWPROT      <= CH3_M_AXI_AWPROT ;
            M_AXI_AWQOS       <= CH3_M_AXI_AWQOS  ;
            M_AXI_AWUSER      <= CH3_M_AXI_AWUSER ;
            M_AXI_AWVALID     <= CH3_M_AXI_AWVALID;
            CH3_M_AXI_AWREADY <= M_AXI_AWREADY    ;
            M_AXI_WDATA       <= CH3_M_AXI_WDATA  ;
            M_AXI_WSTRB       <= CH3_M_AXI_WSTRB  ;
            M_AXI_WLAST       <= CH3_M_AXI_WLAST  ;
            M_AXI_WUSER       <= CH3_M_AXI_WUSER  ;
            M_AXI_WVALID      <= CH3_M_AXI_WVALID ;
            CH3_M_AXI_WREADY  <= M_AXI_WREADY     ;
            CH3_M_AXI_BID     <= M_AXI_BID        ;
            CH3_M_AXI_BRESP   <= M_AXI_BRESP      ;
            CH3_M_AXI_BUSER   <= M_AXI_BUSER      ;
            CH3_M_AXI_BVALID  <= M_AXI_BVALID     ;
            M_AXI_BREADY      <= CH3_M_AXI_BREADY ;
        end
    end