多通道的AXI仲裁方法【第三版】：互联状态机
参考：
循环优先级仲裁~位屏蔽仲裁算法_循环优先级仲裁器-CSDN博客
真的写出来以后比想象的简单很多~
读仲裁：
1 module Aribe_state_rd #( 2 parameter integer M_AXI_ID_WIDTH = 1 , 3 parameter integer M_AXI_ADDR_WIDTH = 32 , 4 parameter integer M_AXI_DATA_WIDTH = 64 , 5 parameter integer M_AXI_AWUSER_WIDTH = 0 , 6 parameter integer M_AXI_ARUSER_WIDTH = 0 , 7 parameter integer M_AXI_WUSER_WIDTH = 0 , 8 parameter integer M_AXI_RUSER_WIDTH = 0 , 9 parameter integer M_AXI_BUSER_WIDTH = 0 10 )( 11 input wire I_clk , 12 input wire I_Rst_n , 13 //Port 14 //ch0 15 input wire I_ch0_req , 16 input wire I_ch0_start , 17 input wire I_ch0_end , 18 output wire O_ch0_vaild , 19 //ch1 20 input wire I_ch1_req , 21 input wire I_ch1_start , 22 input wire I_ch1_end , 23 output wire O_ch1_vaild , 24 //ch2 25 input wire I_ch2_req , 26 input wire I_ch2_start , 27 input wire I_ch2_end , 28 output wire O_ch2_vaild , 29 //ch3 30 input wire I_ch3_req , 31 input wire I_ch3_start , 32 input wire I_ch3_end , 33 output wire O_ch3_vaild , 34 //CH0 35 input wire [M_AXI_ID_WIDTH-1 : 0] CH0_M_AXI_ARID , 36 input wire [M_AXI_ADDR_WIDTH-1 : 0] CH0_M_AXI_ARADDR , 37 input wire [7 : 0] CH0_M_AXI_ARLEN , 38 input wire [2 : 0] CH0_M_AXI_ARSIZE , 39 input wire [1 : 0] CH0_M_AXI_ARBURST , 40 input wire CH0_M_AXI_ARLOCK , 41 input wire [3 : 0] CH0_M_AXI_ARCACHE , 42 input wire [2 : 0] CH0_M_AXI_ARPROT , 43 input wire [3 : 0] CH0_M_AXI_ARQOS , 44 input wire [M_AXI_ARUSER_WIDTH-1 : 0] CH0_M_AXI_ARUSER , 45 input wire CH0_M_AXI_ARVALID , 46 output reg CH0_M_AXI_ARREADY , 47 48 output reg [M_AXI_ID_WIDTH-1 : 0] CH0_M_AXI_RID , 49 output reg [M_AXI_DATA_WIDTH-1 : 0] CH0_M_AXI_RDATA , 50 output reg [1 : 0] CH0_M_AXI_RRESP , 51 output reg CH0_M_AXI_RLAST , 52 output reg [M_AXI_RUSER_WIDTH-1 : 0] CH0_M_AXI_RUSER , 53 output reg CH0_M_AXI_RVALID , 54 input wire CH0_M_AXI_RREADY , 55 //CH1 56 input wire [M_AXI_ID_WIDTH-1 : 0] CH1_M_AXI_ARID , 57 input wire [M_AXI_ADDR_WIDTH-1 : 0] CH1_M_AXI_ARADDR , 58 input wire [7 : 0] CH1_M_AXI_ARLEN , 59 input wire [2 : 0] CH1_M_AXI_ARSIZE , 60 input wire [1 : 0] CH1_M_AXI_ARBURST , 61 input wire CH1_M_AXI_ARLOCK , 62 input wire [3 : 0] CH1_M_AXI_ARCACHE , 63 input wire [2 : 0] CH1_M_AXI_ARPROT , 64 input wire [3 : 0] CH1_M_AXI_ARQOS , 65 input wire [M_AXI_ARUSER_WIDTH-1 : 0] CH1_M_AXI_ARUSER , 66 input wire CH1_M_AXI_ARVALID , 67 output reg CH1_M_AXI_ARREADY , 68 69 output reg [M_AXI_ID_WIDTH-1 : 0] CH1_M_AXI_RID , 70 output reg [M_AXI_DATA_WIDTH-1 : 0] CH1_M_AXI_RDATA , 71 output reg [1 : 0] CH1_M_AXI_RRESP , 72 output reg CH1_M_AXI_RLAST , 73 output reg [M_AXI_RUSER_WIDTH-1 : 0] CH1_M_AXI_RUSER , 74 output reg CH1_M_AXI_RVALID , 75 input wire CH1_M_AXI_RREADY , 76 //CH2 77 input wire [M_AXI_ID_WIDTH-1 : 0] CH2_M_AXI_ARID , 78 input wire [M_AXI_ADDR_WIDTH-1 : 0] CH2_M_AXI_ARADDR , 79 input wire [7 : 0] CH2_M_AXI_ARLEN , 80 input wire [2 : 0] CH2_M_AXI_ARSIZE , 81 input wire [1 : 0] CH2_M_AXI_ARBURST , 82 input wire CH2_M_AXI_ARLOCK , 83 input wire [3 : 0] CH2_M_AXI_ARCACHE , 84 input wire [2 : 0] CH2_M_AXI_ARPROT , 85 input wire [3 : 0] CH2_M_AXI_ARQOS , 86 input wire [M_AXI_ARUSER_WIDTH-1 : 0] CH2_M_AXI_ARUSER , 87 input wire CH2_M_AXI_ARVALID , 88 output reg CH2_M_AXI_ARREADY , 89 90 output reg [M_AXI_ID_WIDTH-1 : 0] CH2_M_AXI_RID , 91 output reg [M_AXI_DATA_WIDTH-1 : 0] CH2_M_AXI_RDATA , 92 output reg [1 : 0] CH2_M_AXI_RRESP , 93 output reg CH2_M_AXI_RLAST , 94 output reg [M_AXI_RUSER_WIDTH-1 : 0] CH2_M_AXI_RUSER , 95 output reg CH2_M_AXI_RVALID , 96 input wire CH2_M_AXI_RREADY , 97 //CH3 98 input wire [M_AXI_ID_WIDTH-1 : 0] CH3_M_AXI_ARID , 99 input wire [M_AXI_ADDR_WIDTH-1 : 0] CH3_M_AXI_ARADDR , 100 input wire [7 : 0] CH3_M_AXI_ARLEN , 101 input wire [2 : 0] CH3_M_AXI_ARSIZE , 102 input wire [1 : 0] CH3_M_AXI_ARBURST , 103 input wire CH3_M_AXI_ARLOCK , 104 input wire [3 : 0] CH3_M_AXI_ARCACHE , 105 input wire [2 : 0] CH3_M_AXI_ARPROT , 106 input wire [3 : 0] CH3_M_AXI_ARQOS , 107 input wire [M_AXI_ARUSER_WIDTH-1 : 0] CH3_M_AXI_ARUSER , 108 input wire CH3_M_AXI_ARVALID , 109 output reg CH3_M_AXI_ARREADY , 110 111 output reg [M_AXI_ID_WIDTH-1 : 0] CH3_M_AXI_RID , 112 output reg [M_AXI_DATA_WIDTH-1 : 0] CH3_M_AXI_RDATA , 113 output reg [1 : 0] CH3_M_AXI_RRESP , 114 output reg CH3_M_AXI_RLAST , 115 output reg [M_AXI_RUSER_WIDTH-1 : 0] CH3_M_AXI_RUSER , 116 output reg CH3_M_AXI_RVALID , 117 input wire CH3_M_AXI_RREADY , 118 //result 119 output reg [M_AXI_ID_WIDTH-1 : 0] M_AXI_ARID , 120 output reg [M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR , 121 output reg [7 : 0] M_AXI_ARLEN , 122 output reg [2 : 0] M_AXI_ARSIZE , 123 output reg [1 : 0] M_AXI_ARBURST , 124 output reg M_AXI_ARLOCK , 125 output reg [3 : 0] M_AXI_ARCACHE , 126 output reg [2 : 0] M_AXI_ARPROT , 127 output reg [3 : 0] M_AXI_ARQOS , 128 output reg [M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER , 129 output reg M_AXI_ARVALID , 130 input wire M_AXI_ARREADY , 131 132 input wire [M_AXI_ID_WIDTH-1 : 0] M_AXI_RID , 133 input wire [M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA , 134 input wire [1 : 0] M_AXI_RRESP , 135 input wire M_AXI_RLAST , 136 input wire [M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER , 137 input wire M_AXI_RVALID , 138 output reg M_AXI_RREADY 139 ); 140 141 //-----------------------------------------------------------------// 142 localparam state_idle = 10'b0000_0000_01; 143 localparam state_aribe = 10'b0000_0000_10; 144 145 localparam state_ch0_0 = 10'b0000_0001_00; 146 localparam state_ch0_1 = 10'b0000_0010_00; 147 148 localparam state_ch1_0 = 10'b0000_0100_00; 149 localparam state_ch1_1 = 10'b0000_1000_00; 150 151 localparam state_ch2_0 = 10'b0001_0000_00; 152 localparam state_ch2_1 = 10'b0010_0000_00; 153 154 localparam state_ch3_0 = 10'b0100_0000_00; 155 localparam state_ch3_1 = 10'b1000_0000_00; 156 157 //-----------------------------------------------------------------// 158 //req 159 //step.0 160 wire [3:0] single_req_Concat ; 161 reg [7:0] double_req_Concat ; 162 //step.1 163 reg [7:0] S1_req_Concat ; 164 //step.2 165 reg [7:0] S2_req_Concat ; 166 //step.3 167 wire [3:0] S3_req_Concat ; 168 //aribe 169 wire aribe_start ; 170 wire aribe_step ; 171 reg aribe_cycle ; 172 reg [3:0] aribe_value ; 173 //step 174 reg [3:0] step ; 175 //state 176 reg [9:0] state ; 177 wire aribe_ch0_end ; 178 wire aribe_ch1_end ; 179 wire aribe_ch2_end ; 180 wire aribe_ch3_end ; 181 //req vaild 182 reg reg_ch0_vaild ; 183 reg reg_ch1_vaild ; 184 reg reg_ch2_vaild ; 185 reg reg_ch3_vaild ; 186 //start 187 reg r1_ch0_start ; 188 reg r2_ch0_start ; 189 190 reg r1_ch1_start ; 191 reg r2_ch1_start ; 192 193 reg r1_ch2_start ; 194 reg r2_ch2_start ; 195 196 reg r1_ch3_start ; 197 reg r2_ch3_start ; 198 //-----------------------------------------------------------------// 199 assign single_req_Concat = {I_ch3_req, I_ch2_req, I_ch1_req, I_ch0_req}; 200 assign aribe_start = |single_req_Concat; 201 assign aribe_step = (aribe_start == 1'b1 && aribe_cycle == 1'b0); 202 203 assign aribe_ch0_end = (I_ch0_end == 1'b1)&&(state == state_ch0_1); 204 assign aribe_ch1_end = (I_ch1_end == 1'b1)&&(state == state_ch1_1); 205 assign aribe_ch2_end = (I_ch2_end == 1'b1)&&(state == state_ch2_1); 206 assign aribe_ch3_end = (I_ch3_end == 1'b1)&&(state == state_ch3_1); 207 208 assign O_ch0_vaild = reg_ch0_vaild; 209 assign O_ch1_vaild = reg_ch1_vaild; 210 assign O_ch2_vaild = reg_ch2_vaild; 211 assign O_ch3_vaild = reg_ch3_vaild; 212 213 always @(posedge I_clk) begin 214 step[3:0] <= {step[2:0],aribe_step}; 215 end 216 217 // Pose 218 always @(posedge I_clk) begin 219 {r2_ch0_start,r1_ch0_start} <= {r1_ch0_start,I_ch0_start}; 220 {r2_ch1_start,r1_ch1_start} <= {r1_ch1_start,I_ch1_start}; 221 {r2_ch2_start,r1_ch2_start} <= {r1_ch2_start,I_ch2_start}; 222 {r2_ch3_start,r1_ch3_start} <= {r1_ch3_start,I_ch3_start}; 223 end 224 225 // aribe_cycle 226 always @(posedge I_clk) begin 227 if(I_Rst_n == 1'b0) begin 228 aribe_cycle <= 1'b0; 229 end else if(aribe_ch0_end|aribe_ch1_end|aribe_ch2_end|aribe_ch3_end) begin 230 aribe_cycle <= 1'b0; 231 end else if(aribe_start == 1'b1 && aribe_cycle == 1'b0 && state == state_idle) begin 232 aribe_cycle <= 1'b1; 233 end else begin 234 aribe_cycle <= aribe_cycle; 235 end 236 end 237 238 // step.0 239 always @(posedge I_clk) begin 240 if(I_Rst_n == 1'b0) begin 241 double_req_Concat <= 'd0; 242 end else if(aribe_step == 1'b1 && step[0] == 1'b0) begin 243 double_req_Concat <= {2{I_ch3_req, I_ch2_req, I_ch1_req, I_ch0_req}}; 244 end else begin 245 double_req_Concat <= double_req_Concat; 246 end 247 end 248 249 // step.1 250 always @(posedge I_clk) begin 251 if(I_Rst_n == 1'b0) begin 252 S1_req_Concat <= 'd0; 253 end else if(step[0] == 1'b1 && step[1] == 1'b0) begin 254 S1_req_Concat <= ~(double_req_Concat - {4'b0,aribe_value}); 255 end else begin 256 S1_req_Concat <= S1_req_Concat; 257 end 258 end 259 260 // step.2 261 always @(posedge I_clk) begin 262 if(I_Rst_n == 1'b0) begin 263 S2_req_Concat <= 'd0; 264 end else if(step[1] == 1'b1 && step[2] == 1'b0) begin 265 S2_req_Concat <= (S1_req_Concat & double_req_Concat); 266 end else begin 267 S2_req_Concat <= S2_req_Concat; 268 end 269 end 270 271 assign S3_req_Concat = ((S2_req_Concat[3:0])|(S2_req_Concat[7:4])); 272 273 // aribe_value 274 always @(posedge I_clk) begin 275 if(I_Rst_n == 1'b0) begin 276 aribe_value <= {3'b0,1'b1}; 277 end else if(aribe_value[3] == 1'b1 && step[0] == 1'b1 && step[1] == 1'b0) begin 278 aribe_value <= {3'b0,1'b1}; 279 end else if(step[0] == 1'b1 && step[1] == 1'b0) begin 280 aribe_value <= aribe_value << 1; 281 end else begin 282 aribe_value <= aribe_value; 283 end 284 end 285 286 //req 287 //ch0 288 always @(posedge I_clk) begin 289 if(I_Rst_n == 1'b0) begin 290 reg_ch0_vaild <= 1'b0; 291 end else if(state == state_ch0_0 && (r1_ch0_start == 1'b1 && r2_ch0_start == 1'b0)) begin 292 reg_ch0_vaild <= 1'b0; 293 end else if(state == state_ch0_0 && reg_ch0_vaild == 1'b0) begin 294 reg_ch0_vaild <= 1'b1; 295 end 296 end 297 //ch1 298 always @(posedge I_clk) begin 299 if(I_Rst_n == 1'b0) begin 300 reg_ch1_vaild <= 1'b0; 301 end else if(state == state_ch1_0 && (r1_ch1_start == 1'b1 && r2_ch1_start == 1'b0)) begin 302 reg_ch1_vaild <= 1'b0; 303 end else if(state == state_ch1_0 && reg_ch1_vaild == 1'b0) begin 304 reg_ch1_vaild <= 1'b1; 305 end 306 end 307 //ch2 308 always @(posedge I_clk) begin 309 if(I_Rst_n == 1'b0) begin 310 reg_ch2_vaild <= 1'b0; 311 end else if(state == state_ch2_0 && (r1_ch2_start == 1'b1 && r2_ch2_start == 1'b0)) begin 312 reg_ch2_vaild <= 1'b0; 313 end else if(state == state_ch2_0 && reg_ch2_vaild == 1'b0) begin 314 reg_ch2_vaild <= 1'b1; 315 end 316 end 317 //ch3 318 always @(posedge I_clk) begin 319 if(I_Rst_n == 1'b0) begin 320 reg_ch3_vaild <= 1'b0; 321 end else if(state == state_ch3_0 && (r1_ch3_start == 1'b1 && r2_ch3_start == 1'b0)) begin 322 reg_ch3_vaild <= 1'b0; 323 end else if(state == state_ch3_0 && reg_ch3_vaild == 1'b0) begin 324 reg_ch3_vaild <= 1'b1; 325 end 326 end 327 328 //state 329 always @(posedge I_clk) begin 330 if(I_Rst_n == 1'b0) begin 331 state <= state_idle; 332 end else begin 333 case (state) 334 state_idle: begin 335 if(aribe_start == 1'b1 && aribe_cycle == 1'b0) begin 336 state <= state_aribe; 337 end else begin 338 state <= state_idle; 339 end 340 end 341 state_aribe:begin 342 if(step[2] == 1'b1 && step[3] == 1'b0) begin 343 case (S3_req_Concat) 344 4'b0001:begin 345 state <= state_ch0_0; 346 end 347 4'b0010:begin 348 state <= state_ch1_0; 349 end 350 4'b0100:begin 351 state <= state_ch2_0; 352 end 353 4'b1000:begin 354 state <= state_ch3_0; 355 end 356 default: state <= state_aribe; 357 endcase 358 end else begin 359 state <= state_aribe; 360 end 361 end 362 // state.step.0 363 state_ch0_0:begin 364 if((r1_ch0_start == 1'b1 && r2_ch0_start == 1'b0)) begin 365 state <= state_ch0_1; 366 end else begin 367 state <= state_ch0_0; 368 end 369 end 370 state_ch1_0:begin 371 if((r1_ch1_start == 1'b1 && r2_ch1_start == 1'b0)) begin 372 state <= state_ch1_1; 373 end else begin 374 state <= state_ch1_0; 375 end 376 end 377 state_ch2_0:begin 378 if((r1_ch2_start == 1'b1 && r2_ch2_start == 1'b0)) begin 379 state <= state_ch2_1; 380 end else begin 381 state <= state_ch2_0; 382 end 383 end 384 state_ch3_0:begin 385 if((r1_ch3_start == 1'b1 && r2_ch3_start == 1'b0)) begin 386 state <= state_ch3_1; 387 end else begin 388 state <= state_ch3_0; 389 end 390 end 391 392 // state.step.1 393 state_ch0_1:begin 394 if(I_ch0_end == 1'b1) begin 395 state <= state_idle; 396 end else begin 397 state <= state_ch0_1; 398 end 399 end 400 state_ch1_1:begin 401 if(I_ch1_end == 1'b1) begin 402 state <= state_idle; 403 end else begin 404 state <= state_ch1_1; 405 end 406 end 407 state_ch2_1:begin 408 if(I_ch2_end == 1'b1) begin 409 state <= state_idle; 410 end else begin 411 state <= state_ch2_1; 412 end 413 end 414 state_ch3_1:begin 415 if(I_ch3_end == 1'b1) begin 416 state <= state_idle; 417 end else begin 418 state <= state_ch3_1; 419 end 420 end 421 default: begin 422 state <= state_idle; 423 end 424 endcase 425 end 426 end 427 always @(*) begin 428 if(state == state_ch0_0||state == state_ch0_1) begin 429 M_AXI_ARID <= CH0_M_AXI_ARID ; 430 M_AXI_ARADDR <= CH0_M_AXI_ARADDR ; 431 M_AXI_ARLEN <= CH0_M_AXI_ARLEN ; 432 M_AXI_ARSIZE <= CH0_M_AXI_ARSIZE ; 433 M_AXI_ARBURST <= CH0_M_AXI_ARBURST ; 434 M_AXI_ARLOCK <= CH0_M_AXI_ARLOCK ; 435 M_AXI_ARCACHE <= CH0_M_AXI_ARCACHE ; 436 M_AXI_ARPROT <= CH0_M_AXI_ARPROT ; 437 M_AXI_ARQOS <= CH0_M_AXI_ARQOS ; 438 M_AXI_ARUSER <= CH0_M_AXI_ARUSER ; 439 M_AXI_ARVALID <= CH0_M_AXI_ARVALID ; 440 CH0_M_AXI_ARREADY <= M_AXI_ARREADY ; 441 442 CH0_M_AXI_RID <= M_AXI_RID ; 443 CH0_M_AXI_RDATA <= M_AXI_RDATA ; 444 CH0_M_AXI_RRESP <= M_AXI_RRESP ; 445 CH0_M_AXI_RLAST <= M_AXI_RLAST ; 446 CH0_M_AXI_RUSER <= M_AXI_RUSER ; 447 CH0_M_AXI_RVALID <= M_AXI_RVALID ; 448 M_AXI_RREADY <= CH0_M_AXI_RREADY ; 449 end else if(state == state_ch1_0 || state == state_ch1_1) begin 450 M_AXI_ARID <= CH1_M_AXI_ARID ; 451 M_AXI_ARADDR <= CH1_M_AXI_ARADDR ; 452 M_AXI_ARLEN <= CH1_M_AXI_ARLEN ; 453 M_AXI_ARSIZE <= CH1_M_AXI_ARSIZE ; 454 M_AXI_ARBURST <= CH1_M_AXI_ARBURST ; 455 M_AXI_ARLOCK <= CH1_M_AXI_ARLOCK ; 456 M_AXI_ARCACHE <= CH1_M_AXI_ARCACHE ; 457 M_AXI_ARPROT <= CH1_M_AXI_ARPROT ; 458 M_AXI_ARQOS <= CH1_M_AXI_ARQOS ; 459 M_AXI_ARUSER <= CH1_M_AXI_ARUSER ; 460 M_AXI_ARVALID <= CH1_M_AXI_ARVALID ; 461 CH1_M_AXI_ARREADY <= M_AXI_ARREADY ; 462 463 CH1_M_AXI_RID <= M_AXI_RID ; 464 CH1_M_AXI_RDATA <= M_AXI_RDATA ; 465 CH1_M_AXI_RRESP <= M_AXI_RRESP ; 466 CH1_M_AXI_RLAST <= M_AXI_RLAST ; 467 CH1_M_AXI_RUSER <= M_AXI_RUSER ; 468 CH1_M_AXI_RVALID <= M_AXI_RVALID ; 469 M_AXI_RREADY <= CH1_M_AXI_RREADY ; 470 end else if(state == state_ch2_0 || state == state_ch2_1) begin 471 M_AXI_ARID <= CH2_M_AXI_ARID ; 472 M_AXI_ARADDR <= CH2_M_AXI_ARADDR ; 473 M_AXI_ARLEN <= CH2_M_AXI_ARLEN ; 474 M_AXI_ARSIZE <= CH2_M_AXI_ARSIZE ; 475 M_AXI_ARBURST <= CH2_M_AXI_ARBURST ; 476 M_AXI_ARLOCK <= CH2_M_AXI_ARLOCK ; 477 M_AXI_ARCACHE <= CH2_M_AXI_ARCACHE ; 478 M_AXI_ARPROT <= CH2_M_AXI_ARPROT ; 479 M_AXI_ARQOS <= CH2_M_AXI_ARQOS ; 480 M_AXI_ARUSER <= CH2_M_AXI_ARUSER ; 481 M_AXI_ARVALID <= CH2_M_AXI_ARVALID ; 482 CH2_M_AXI_ARREADY <= M_AXI_ARREADY ; 483 484 CH2_M_AXI_RID <= M_AXI_RID ; 485 CH2_M_AXI_RDATA <= M_AXI_RDATA ; 486 CH2_M_AXI_RRESP <= M_AXI_RRESP ; 487 CH2_M_AXI_RLAST <= M_AXI_RLAST ; 488 CH2_M_AXI_RUSER <= M_AXI_RUSER ; 489 CH2_M_AXI_RVALID <= M_AXI_RVALID ; 490 M_AXI_RREADY <= CH2_M_AXI_RREADY ; 491 end else if(state == state_ch3_0 || state == state_ch3_1) begin 492 M_AXI_ARID <= CH3_M_AXI_ARID ; 493 M_AXI_ARADDR <= CH3_M_AXI_ARADDR ; 494 M_AXI_ARLEN <= CH3_M_AXI_ARLEN ; 495 M_AXI_ARSIZE <= CH3_M_AXI_ARSIZE ; 496 M_AXI_ARBURST <= CH3_M_AXI_ARBURST ; 497 M_AXI_ARLOCK <= CH3_M_AXI_ARLOCK ; 498 M_AXI_ARCACHE <= CH3_M_AXI_ARCACHE ; 499 M_AXI_ARPROT <= CH3_M_AXI_ARPROT ; 500 M_AXI_ARQOS <= CH3_M_AXI_ARQOS ; 501 M_AXI_ARUSER <= CH3_M_AXI_ARUSER ; 502 M_AXI_ARVALID <= CH3_M_AXI_ARVALID ; 503 CH3_M_AXI_ARREADY <= M_AXI_ARREADY ; 504 505 CH3_M_AXI_RID <= M_AXI_RID ; 506 CH3_M_AXI_RDATA <= M_AXI_RDATA ; 507 CH3_M_AXI_RRESP <= M_AXI_RRESP ; 508 CH3_M_AXI_RLAST <= M_AXI_RLAST ; 509 CH3_M_AXI_RUSER <= M_AXI_RUSER ; 510 CH3_M_AXI_RVALID <= M_AXI_RVALID ; 511 M_AXI_RREADY <= CH3_M_AXI_RREADY ; 512 end else begin 513 M_AXI_ARID <= CH3_M_AXI_ARID ; 514 M_AXI_ARADDR <= CH3_M_AXI_ARADDR ; 515 M_AXI_ARLEN <= CH3_M_AXI_ARLEN ; 516 M_AXI_ARSIZE <= CH3_M_AXI_ARSIZE ; 517 M_AXI_ARBURST <= CH3_M_AXI_ARBURST ; 518 M_AXI_ARLOCK <= CH3_M_AXI_ARLOCK ; 519 M_AXI_ARCACHE <= CH3_M_AXI_ARCACHE ; 520 M_AXI_ARPROT <= CH3_M_AXI_ARPROT ; 521 M_AXI_ARQOS <= CH3_M_AXI_ARQOS ; 522 M_AXI_ARUSER <= CH3_M_AXI_ARUSER ; 523 M_AXI_ARVALID <= CH3_M_AXI_ARVALID ; 524 CH3_M_AXI_ARREADY <= M_AXI_ARREADY ; 525 526 CH3_M_AXI_RID <= M_AXI_RID ; 527 CH3_M_AXI_RDATA <= M_AXI_RDATA ; 528 CH3_M_AXI_RRESP <= M_AXI_RRESP ; 529 CH3_M_AXI_RLAST <= M_AXI_RLAST ; 530 CH3_M_AXI_RUSER <= M_AXI_RUSER ; 531 CH3_M_AXI_RVALID <= M_AXI_RVALID ; 532 M_AXI_RREADY <= CH3_M_AXI_RREADY ; 533 end 534 end 535 endmodule
写仲裁：
1 module Aribe_state_wr #( 2 parameter integer M_AXI_ID_WIDTH = 1 , 3 parameter integer M_AXI_ADDR_WIDTH = 32 , 4 parameter integer M_AXI_DATA_WIDTH = 64 , 5 parameter integer M_AXI_AWUSER_WIDTH = 0 , 6 parameter integer M_AXI_ARUSER_WIDTH = 0 , 7 parameter integer M_AXI_WUSER_WIDTH = 0 , 8 parameter integer M_AXI_RUSER_WIDTH = 0 , 9 parameter integer M_AXI_BUSER_WIDTH = 0 10 )( 11 input wire I_clk , 12 input wire I_Rst_n , 13 //Port 14 //ch0 15 input wire I_ch0_req , 16 input wire I_ch0_start , 17 input wire I_ch0_end , 18 output wire O_ch0_vaild , 19 //ch1 20 input wire I_ch1_req , 21 input wire I_ch1_start , 22 input wire I_ch1_end , 23 output wire O_ch1_vaild , 24 //ch2 25 input wire I_ch2_req , 26 input wire I_ch2_start , 27 input wire I_ch2_end , 28 output wire O_ch2_vaild , 29 //ch3 30 input wire I_ch3_req , 31 input wire I_ch3_start , 32 input wire I_ch3_end , 33 output wire O_ch3_vaild , 34 //CH0 35 input wire [M_AXI_ID_WIDTH-1 : 0] CH0_M_AXI_AWID , 36 input wire [M_AXI_ADDR_WIDTH-1 : 0] CH0_M_AXI_AWADDR , 37 input wire [7 : 0] CH0_M_AXI_AWLEN , 38 input wire [2 : 0] CH0_M_AXI_AWSIZE , 39 input wire [1 : 0] CH0_M_AXI_AWBURST , 40 input wire CH0_M_AXI_AWLOCK , 41 input wire [3 : 0] CH0_M_AXI_AWCACHE , 42 input wire [2 : 0] CH0_M_AXI_AWPROT , 43 input wire [3 : 0] CH0_M_AXI_AWQOS , 44 input wire [M_AXI_AWUSER_WIDTH-1 : 0] CH0_M_AXI_AWUSER , 45 input wire CH0_M_AXI_AWVALID , 46 output reg CH0_M_AXI_AWREADY , 47 48 input wire [M_AXI_DATA_WIDTH-1 : 0] CH0_M_AXI_WDATA , 49 input wire [M_AXI_DATA_WIDTH/8-1 : 0] CH0_M_AXI_WSTRB , 50 input wire CH0_M_AXI_WLAST , 51 input wire [M_AXI_WUSER_WIDTH-1 : 0] CH0_M_AXI_WUSER , 52 input wire CH0_M_AXI_WVALID , 53 output reg CH0_M_AXI_WREADY , 54 55 output reg [M_AXI_ID_WIDTH-1 : 0] CH0_M_AXI_BID , 56 output reg [1 : 0] CH0_M_AXI_BRESP , 57 output reg [M_AXI_BUSER_WIDTH-1 : 0] CH0_M_AXI_BUSER , 58 output reg CH0_M_AXI_BVALID , 59 input wire CH0_M_AXI_BREADY , 60 //CH1 61 input wire [M_AXI_ID_WIDTH-1 : 0] CH1_M_AXI_AWID , 62 input wire [M_AXI_ADDR_WIDTH-1 : 0] CH1_M_AXI_AWADDR , 63 input wire [7 : 0] CH1_M_AXI_AWLEN , 64 input wire [2 : 0] CH1_M_AXI_AWSIZE , 65 input wire [1 : 0] CH1_M_AXI_AWBURST , 66 input wire CH1_M_AXI_AWLOCK , 67 input wire [3 : 0] CH1_M_AXI_AWCACHE , 68 input wire [2 : 0] CH1_M_AXI_AWPROT , 69 input wire [3 : 0] CH1_M_AXI_AWQOS , 70 input wire [M_AXI_AWUSER_WIDTH-1 : 0] CH1_M_AXI_AWUSER , 71 input wire CH1_M_AXI_AWVALID , 72 output reg CH1_M_AXI_AWREADY , 73 74 input wire [M_AXI_DATA_WIDTH-1 : 0] CH1_M_AXI_WDATA , 75 input wire [M_AXI_DATA_WIDTH/8-1 : 0] CH1_M_AXI_WSTRB , 76 input wire CH1_M_AXI_WLAST , 77 input wire [M_AXI_WUSER_WIDTH-1 : 0] CH1_M_AXI_WUSER , 78 input wire CH1_M_AXI_WVALID , 79 output reg CH1_M_AXI_WREADY , 80 81 output reg [M_AXI_ID_WIDTH-1 : 0] CH1_M_AXI_BID , 82 output reg [1 : 0] CH1_M_AXI_BRESP , 83 output reg [M_AXI_BUSER_WIDTH-1 : 0] CH1_M_AXI_BUSER , 84 output reg CH1_M_AXI_BVALID , 85 input wire CH1_M_AXI_BREADY , 86 //CH2 87 input wire [M_AXI_ID_WIDTH-1 : 0] CH2_M_AXI_AWID , 88 input wire [M_AXI_ADDR_WIDTH-1 : 0] CH2_M_AXI_AWADDR , 89 input wire [7 : 0] CH2_M_AXI_AWLEN , 90 input wire [2 : 0] CH2_M_AXI_AWSIZE , 91 input wire [1 : 0] CH2_M_AXI_AWBURST , 92 input wire CH2_M_AXI_AWLOCK , 93 input wire [3 : 0] CH2_M_AXI_AWCACHE , 94 input wire [2 : 0] CH2_M_AXI_AWPROT , 95 input wire [3 : 0] CH2_M_AXI_AWQOS , 96 input wire [M_AXI_AWUSER_WIDTH-1 : 0] CH2_M_AXI_AWUSER , 97 input wire CH2_M_AXI_AWVALID , 98 output reg CH2_M_AXI_AWREADY , 99 100 input wire [M_AXI_DATA_WIDTH-1 : 0] CH2_M_AXI_WDATA , 101 input wire [M_AXI_DATA_WIDTH/8-1 : 0] CH2_M_AXI_WSTRB , 102 input wire CH2_M_AXI_WLAST , 103 input wire [M_AXI_WUSER_WIDTH-1 : 0] CH2_M_AXI_WUSER , 104 input wire CH2_M_AXI_WVALID , 105 output reg CH2_M_AXI_WREADY , 106 107 output reg [M_AXI_ID_WIDTH-1 : 0] CH2_M_AXI_BID , 108 output reg [1 : 0] CH2_M_AXI_BRESP , 109 output reg [M_AXI_BUSER_WIDTH-1 : 0] CH2_M_AXI_BUSER , 110 output reg CH2_M_AXI_BVALID , 111 input wire CH2_M_AXI_BREADY , 112 //CH3 113 input wire [M_AXI_ID_WIDTH-1 : 0] CH3_M_AXI_AWID , 114 input wire [M_AXI_ADDR_WIDTH-1 : 0] CH3_M_AXI_AWADDR , 115 input wire [7 : 0] CH3_M_AXI_AWLEN , 116 input wire [2 : 0] CH3_M_AXI_AWSIZE , 117 input wire [1 : 0] CH3_M_AXI_AWBURST , 118 input wire CH3_M_AXI_AWLOCK , 119 input wire [3 : 0] CH3_M_AXI_AWCACHE , 120 input wire [2 : 0] CH3_M_AXI_AWPROT , 121 input wire [3 : 0] CH3_M_AXI_AWQOS , 122 input wire [M_AXI_AWUSER_WIDTH-1 : 0] CH3_M_AXI_AWUSER , 123 input wire CH3_M_AXI_AWVALID , 124 output reg CH3_M_AXI_AWREADY , 125 126 input wire [M_AXI_DATA_WIDTH-1 : 0] CH3_M_AXI_WDATA , 127 input wire [M_AXI_DATA_WIDTH/8-1 : 0] CH3_M_AXI_WSTRB , 128 input wire CH3_M_AXI_WLAST , 129 input wire [M_AXI_WUSER_WIDTH-1 : 0] CH3_M_AXI_WUSER , 130 input wire CH3_M_AXI_WVALID , 131 output reg CH3_M_AXI_WREADY , 132 133 output reg [M_AXI_ID_WIDTH-1 : 0] CH3_M_AXI_BID , 134 output reg [1 : 0] CH3_M_AXI_BRESP , 135 output reg [M_AXI_BUSER_WIDTH-1 : 0] CH3_M_AXI_BUSER , 136 output reg CH3_M_AXI_BVALID , 137 input wire CH3_M_AXI_BREADY , 138 //result 139 output reg [M_AXI_ID_WIDTH-1 : 0] M_AXI_AWID , 140 output reg [M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR , 141 output reg [7 : 0] M_AXI_AWLEN , 142 output reg [2 : 0] M_AXI_AWSIZE , 143 output reg [1 : 0] M_AXI_AWBURST , 144 output reg M_AXI_AWLOCK , 145 output reg [3 : 0] M_AXI_AWCACHE , 146 output reg [2 : 0] M_AXI_AWPROT , 147 output reg [3 : 0] M_AXI_AWQOS , 148 output reg [M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER , 149 output reg M_AXI_AWVALID , 150 input wire M_AXI_AWREADY , 151 152 output reg [M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA , 153 output reg [M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB , 154 output reg M_AXI_WLAST , 155 output reg [M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER , 156 output reg M_AXI_WVALID , 157 input wire M_AXI_WREADY , 158 159 input wire [M_AXI_ID_WIDTH-1 : 0] M_AXI_BID , 160 input wire [1 : 0] M_AXI_BRESP , 161 input wire [M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER , 162 input wire M_AXI_BVALID , 163 output reg M_AXI_BREADY 164 ); 165 166 //-----------------------------------------------------------------// 167 localparam state_idle = 10'b0000_0000_01; 168 localparam state_aribe = 10'b0000_0000_10; 169 170 localparam state_ch0_0 = 10'b0000_0001_00; 171 localparam state_ch0_1 = 10'b0000_0010_00; 172 173 localparam state_ch1_0 = 10'b0000_0100_00; 174 localparam state_ch1_1 = 10'b0000_1000_00; 175 176 localparam state_ch2_0 = 10'b0001_0000_00; 177 localparam state_ch2_1 = 10'b0010_0000_00; 178 179 localparam state_ch3_0 = 10'b0100_0000_00; 180 localparam state_ch3_1 = 10'b1000_0000_00; 181 182 //-----------------------------------------------------------------// 183 //req 184 //step.0 185 wire [3:0] single_req_Concat ; 186 reg [7:0] double_req_Concat ; 187 //step.1 188 reg [7:0] S1_req_Concat ; 189 //step.2 190 reg [7:0] S2_req_Concat ; 191 //step.3 192 wire [3:0] S3_req_Concat ; 193 //aribe 194 wire aribe_start ; 195 wire aribe_step ; 196 reg aribe_cycle ; 197 reg [3:0] aribe_value ; 198 //step 199 reg [3:0] step ; 200 //state 201 reg [9:0] state ; 202 wire aribe_ch0_end ; 203 wire aribe_ch1_end ; 204 wire aribe_ch2_end ; 205 wire aribe_ch3_end ; 206 //req vaild 207 reg reg_ch0_vaild ; 208 reg reg_ch1_vaild ; 209 reg reg_ch2_vaild ; 210 reg reg_ch3_vaild ; 211 //start 212 reg r1_ch0_start ; 213 reg r2_ch0_start ; 214 215 reg r1_ch1_start ; 216 reg r2_ch1_start ; 217 218 reg r1_ch2_start ; 219 reg r2_ch2_start ; 220 221 reg r1_ch3_start ; 222 reg r2_ch3_start ; 223 //-----------------------------------------------------------------// 224 assign single_req_Concat = {I_ch3_req, I_ch2_req, I_ch1_req, I_ch0_req}; 225 assign aribe_start = |single_req_Concat; 226 assign aribe_step = (aribe_start == 1'b1 && aribe_cycle == 1'b0); 227 228 assign aribe_ch0_end = (I_ch0_end == 1'b1)&&(state == state_ch0_1); 229 assign aribe_ch1_end = (I_ch1_end == 1'b1)&&(state == state_ch1_1); 230 assign aribe_ch2_end = (I_ch2_end == 1'b1)&&(state == state_ch2_1); 231 assign aribe_ch3_end = (I_ch3_end == 1'b1)&&(state == state_ch3_1); 232 233 assign O_ch0_vaild = reg_ch0_vaild; 234 assign O_ch1_vaild = reg_ch1_vaild; 235 assign O_ch2_vaild = reg_ch2_vaild; 236 assign O_ch3_vaild = reg_ch3_vaild; 237 238 always @(posedge I_clk) begin 239 step[3:0] <= {step[2:0],aribe_step}; 240 end 241 242 // Pose 243 always @(posedge I_clk) begin 244 {r2_ch0_start,r1_ch0_start} <= {r1_ch0_start,I_ch0_start}; 245 {r2_ch1_start,r1_ch1_start} <= {r1_ch1_start,I_ch1_start}; 246 {r2_ch2_start,r1_ch2_start} <= {r1_ch2_start,I_ch2_start}; 247 {r2_ch3_start,r1_ch3_start} <= {r1_ch3_start,I_ch3_start}; 248 end 249 250 // aribe_cycle 251 always @(posedge I_clk) begin 252 if(I_Rst_n == 1'b0) begin 253 aribe_cycle <= 1'b0; 254 end else if(aribe_ch0_end|aribe_ch1_end|aribe_ch2_end|aribe_ch3_end) begin 255 aribe_cycle <= 1'b0; 256 end else if(aribe_start == 1'b1 && aribe_cycle == 1'b0 && state == state_idle) begin 257 aribe_cycle <= 1'b1; 258 end else begin 259 aribe_cycle <= aribe_cycle; 260 end 261 end 262 263 // step.0 264 always @(posedge I_clk) begin 265 if(I_Rst_n == 1'b0) begin 266 double_req_Concat <= 'd0; 267 end else if(aribe_step == 1'b1 && step[0] == 1'b0) begin 268 double_req_Concat <= {2{I_ch3_req, I_ch2_req, I_ch1_req, I_ch0_req}}; 269 end else begin 270 double_req_Concat <= double_req_Concat; 271 end 272 end 273 274 // step.1 275 always @(posedge I_clk) begin 276 if(I_Rst_n == 1'b0) begin 277 S1_req_Concat <= 'd0; 278 end else if(step[0] == 1'b1 && step[1] == 1'b0) begin 279 S1_req_Concat <= ~(double_req_Concat - {4'b0,aribe_value}); 280 end else begin 281 S1_req_Concat <= S1_req_Concat; 282 end 283 end 284 285 // step.2 286 always @(posedge I_clk) begin 287 if(I_Rst_n == 1'b0) begin 288 S2_req_Concat <= 'd0; 289 end else if(step[1] == 1'b1 && step[2] == 1'b0) begin 290 S2_req_Concat <= (S1_req_Concat & double_req_Concat); 291 end else begin 292 S2_req_Concat <= S2_req_Concat; 293 end 294 end 295 296 assign S3_req_Concat = ((S2_req_Concat[3:0])|(S2_req_Concat[7:4])); 297 298 // aribe_value 299 always @(posedge I_clk) begin 300 if(I_Rst_n == 1'b0) begin 301 aribe_value <= {3'b0,1'b1}; 302 end else if(aribe_value[3] == 1'b1 && step[0] == 1'b1 && step[1] == 1'b0) begin 303 aribe_value <= {3'b0,1'b1}; 304 end else if(step[0] == 1'b1 && step[1] == 1'b0) begin 305 aribe_value <= aribe_value << 1; 306 end else begin 307 aribe_value <= aribe_value; 308 end 309 end 310 311 //req 312 //ch0 313 always @(posedge I_clk) begin 314 if(I_Rst_n == 1'b0) begin 315 reg_ch0_vaild <= 1'b0; 316 end else if(state == state_ch0_0 && (r1_ch0_start == 1'b1 && r2_ch0_start == 1'b0)) begin 317 reg_ch0_vaild <= 1'b0; 318 end else if(state == state_ch0_0 && reg_ch0_vaild == 1'b0) begin 319 reg_ch0_vaild <= 1'b1; 320 end 321 end 322 //ch1 323 always @(posedge I_clk) begin 324 if(I_Rst_n == 1'b0) begin 325 reg_ch1_vaild <= 1'b0; 326 end else if(state == state_ch1_0 && (r1_ch1_start == 1'b1 && r2_ch1_start == 1'b0)) begin 327 reg_ch1_vaild <= 1'b0; 328 end else if(state == state_ch1_0 && reg_ch1_vaild == 1'b0) begin 329 reg_ch1_vaild <= 1'b1; 330 end 331 end 332 //ch2 333 always @(posedge I_clk) begin 334 if(I_Rst_n == 1'b0) begin 335 reg_ch2_vaild <= 1'b0; 336 end else if(state == state_ch2_0 && (r1_ch2_start == 1'b1 && r2_ch2_start == 1'b0)) begin 337 reg_ch2_vaild <= 1'b0; 338 end else if(state == state_ch2_0 && reg_ch2_vaild == 1'b0) begin 339 reg_ch2_vaild <= 1'b1; 340 end 341 end 342 //ch3 343 always @(posedge I_clk) begin 344 if(I_Rst_n == 1'b0) begin 345 reg_ch3_vaild <= 1'b0; 346 end else if(state == state_ch3_0 && (r1_ch3_start == 1'b1 && r2_ch3_start == 1'b0)) begin 347 reg_ch3_vaild <= 1'b0; 348 end else if(state == state_ch3_0 && reg_ch3_vaild == 1'b0) begin 349 reg_ch3_vaild <= 1'b1; 350 end 351 end 352 353 //state 354 always @(posedge I_clk) begin 355 if(I_Rst_n == 1'b0) begin 356 state <= state_idle; 357 end else begin 358 case (state) 359 state_idle: begin 360 if(aribe_start == 1'b1 && aribe_cycle == 1'b0) begin 361 state <= state_aribe; 362 end else begin 363 state <= state_idle; 364 end 365 end 366 state_aribe:begin 367 if(step[2] == 1'b1 && step[3] == 1'b0) begin 368 case (S3_req_Concat) 369 4'b0001:begin 370 state <= state_ch0_0; 371 end 372 4'b0010:begin 373 state <= state_ch1_0; 374 end 375 4'b0100:begin 376 state <= state_ch2_0; 377 end 378 4'b1000:begin 379 state <= state_ch3_0; 380 end 381 default: state <= state_aribe; 382 endcase 383 end else begin 384 state <= state_aribe; 385 end 386 end 387 // state.step.0 388 state_ch0_0:begin 389 if((r1_ch0_start == 1'b1 && r2_ch0_start == 1'b0)) begin 390 state <= state_ch0_1; 391 end else begin 392 state <= state_ch0_0; 393 end 394 end 395 state_ch1_0:begin 396 if((r1_ch1_start == 1'b1 && r2_ch1_start == 1'b0)) begin 397 state <= state_ch1_1; 398 end else begin 399 state <= state_ch1_0; 400 end 401 end 402 state_ch2_0:begin 403 if((r1_ch2_start == 1'b1 && r2_ch2_start == 1'b0)) begin 404 state <= state_ch2_1; 405 end else begin 406 state <= state_ch2_0; 407 end 408 end 409 state_ch3_0:begin 410 if((r1_ch3_start == 1'b1 && r2_ch3_start == 1'b0)) begin 411 state <= state_ch3_1; 412 end else begin 413 state <= state_ch3_0; 414 end 415 end 416 417 // state.step.1 418 state_ch0_1:begin 419 if(I_ch0_end == 1'b1) begin 420 state <= state_idle; 421 end else begin 422 state <= state_ch0_1; 423 end 424 end 425 state_ch1_1:begin 426 if(I_ch1_end == 1'b1) begin 427 state <= state_idle; 428 end else begin 429 state <= state_ch1_1; 430 end 431 end 432 state_ch2_1:begin 433 if(I_ch2_end == 1'b1) begin 434 state <= state_idle; 435 end else begin 436 state <= state_ch2_1; 437 end 438 end 439 state_ch3_1:begin 440 if(I_ch3_end == 1'b1) begin 441 state <= state_idle; 442 end else begin 443 state <= state_ch3_1; 444 end 445 end 446 default: begin 447 state <= state_idle; 448 end 449 endcase 450 end 451 end 452 453 always @(*) begin 454 if(state == state_ch0_0||state == state_ch0_1) begin 455 M_AXI_AWID <= CH0_M_AXI_AWID ; 456 M_AXI_AWADDR <= CH0_M_AXI_AWADDR ; 457 M_AXI_AWLEN <= CH0_M_AXI_AWLEN ; 458 M_AXI_AWSIZE <= CH0_M_AXI_AWSIZE ; 459 M_AXI_AWBURST <= CH0_M_AXI_AWBURST; 460 M_AXI_AWLOCK <= CH0_M_AXI_AWLOCK ; 461 M_AXI_AWCACHE <= CH0_M_AXI_AWCACHE; 462 M_AXI_AWPROT <= CH0_M_AXI_AWPROT ; 463 M_AXI_AWQOS <= CH0_M_AXI_AWQOS ; 464 M_AXI_AWUSER <= CH0_M_AXI_AWUSER ; 465 M_AXI_AWVALID <= CH0_M_AXI_AWVALID; 466 CH0_M_AXI_AWREADY <= M_AXI_AWREADY ; 467 M_AXI_WDATA <= CH0_M_AXI_WDATA ; 468 M_AXI_WSTRB <= CH0_M_AXI_WSTRB ; 469 M_AXI_WLAST <= CH0_M_AXI_WLAST ; 470 M_AXI_WUSER <= CH0_M_AXI_WUSER ; 471 M_AXI_WVALID <= CH0_M_AXI_WVALID ; 472 CH0_M_AXI_WREADY <= M_AXI_WREADY ; 473 CH0_M_AXI_BID <= M_AXI_BID ; 474 CH0_M_AXI_BRESP <= M_AXI_BRESP ; 475 CH0_M_AXI_BUSER <= M_AXI_BUSER ; 476 CH0_M_AXI_BVALID <= M_AXI_BVALID ; 477 M_AXI_BREADY <= CH0_M_AXI_BREADY ; 478 end else if(state == state_ch1_0 || state == state_ch1_1) begin 479 M_AXI_AWID <= CH1_M_AXI_AWID ; 480 M_AXI_AWADDR <= CH1_M_AXI_AWADDR ; 481 M_AXI_AWLEN <= CH1_M_AXI_AWLEN ; 482 M_AXI_AWSIZE <= CH1_M_AXI_AWSIZE ; 483 M_AXI_AWBURST <= CH1_M_AXI_AWBURST; 484 M_AXI_AWLOCK <= CH1_M_AXI_AWLOCK ; 485 M_AXI_AWCACHE <= CH1_M_AXI_AWCACHE; 486 M_AXI_AWPROT <= CH1_M_AXI_AWPROT ; 487 M_AXI_AWQOS <= CH1_M_AXI_AWQOS ; 488 M_AXI_AWUSER <= CH1_M_AXI_AWUSER ; 489 M_AXI_AWVALID <= CH1_M_AXI_AWVALID; 490 CH1_M_AXI_AWREADY <= M_AXI_AWREADY ; 491 M_AXI_WDATA <= CH1_M_AXI_WDATA ; 492 M_AXI_WSTRB <= CH1_M_AXI_WSTRB ; 493 M_AXI_WLAST <= CH1_M_AXI_WLAST ; 494 M_AXI_WUSER <= CH1_M_AXI_WUSER ; 495 M_AXI_WVALID <= CH1_M_AXI_WVALID ; 496 CH1_M_AXI_WREADY <= M_AXI_WREADY ; 497 CH1_M_AXI_BID <= M_AXI_BID ; 498 CH1_M_AXI_BRESP <= M_AXI_BRESP ; 499 CH1_M_AXI_BUSER <= M_AXI_BUSER ; 500 CH1_M_AXI_BVALID <= M_AXI_BVALID ; 501 M_AXI_BREADY <= CH1_M_AXI_BREADY ; 502 end else if(state == state_ch2_0 || state == state_ch2_1) begin 503 M_AXI_AWID <= CH2_M_AXI_AWID ; 504 M_AXI_AWADDR <= CH2_M_AXI_AWADDR ; 505 M_AXI_AWLEN <= CH2_M_AXI_AWLEN ; 506 M_AXI_AWSIZE <= CH2_M_AXI_AWSIZE ; 507 M_AXI_AWBURST <= CH2_M_AXI_AWBURST; 508 M_AXI_AWLOCK <= CH2_M_AXI_AWLOCK ; 509 M_AXI_AWCACHE <= CH2_M_AXI_AWCACHE; 510 M_AXI_AWPROT <= CH2_M_AXI_AWPROT ; 511 M_AXI_AWQOS <= CH2_M_AXI_AWQOS ; 512 M_AXI_AWUSER <= CH2_M_AXI_AWUSER ; 513 M_AXI_AWVALID <= CH2_M_AXI_AWVALID; 514 CH2_M_AXI_AWREADY <= M_AXI_AWREADY ; 515 M_AXI_WDATA <= CH2_M_AXI_WDATA ; 516 M_AXI_WSTRB <= CH2_M_AXI_WSTRB ; 517 M_AXI_WLAST <= CH2_M_AXI_WLAST ; 518 M_AXI_WUSER <= CH2_M_AXI_WUSER ; 519 M_AXI_WVALID <= CH2_M_AXI_WVALID ; 520 CH2_M_AXI_WREADY <= M_AXI_WREADY ; 521 CH2_M_AXI_BID <= M_AXI_BID ; 522 CH2_M_AXI_BRESP <= M_AXI_BRESP ; 523 CH2_M_AXI_BUSER <= M_AXI_BUSER ; 524 CH2_M_AXI_BVALID <= M_AXI_BVALID ; 525 M_AXI_BREADY <= CH2_M_AXI_BREADY ; 526 end else if(state == state_ch3_0 || state == state_ch3_1) begin 527 M_AXI_AWID <= CH3_M_AXI_AWID ; 528 M_AXI_AWADDR <= CH3_M_AXI_AWADDR ; 529 M_AXI_AWLEN <= CH3_M_AXI_AWLEN ; 530 M_AXI_AWSIZE <= CH3_M_AXI_AWSIZE ; 531 M_AXI_AWBURST <= CH3_M_AXI_AWBURST; 532 M_AXI_AWLOCK <= CH3_M_AXI_AWLOCK ; 533 M_AXI_AWCACHE <= CH3_M_AXI_AWCACHE; 534 M_AXI_AWPROT <= CH3_M_AXI_AWPROT ; 535 M_AXI_AWQOS <= CH3_M_AXI_AWQOS ; 536 M_AXI_AWUSER <= CH3_M_AXI_AWUSER ; 537 M_AXI_AWVALID <= CH3_M_AXI_AWVALID; 538 CH3_M_AXI_AWREADY <= M_AXI_AWREADY ; 539 M_AXI_WDATA <= CH3_M_AXI_WDATA ; 540 M_AXI_WSTRB <= CH3_M_AXI_WSTRB ; 541 M_AXI_WLAST <= CH3_M_AXI_WLAST ; 542 M_AXI_WUSER <= CH3_M_AXI_WUSER ; 543 M_AXI_WVALID <= CH3_M_AXI_WVALID ; 544 CH3_M_AXI_WREADY <= M_AXI_WREADY ; 545 CH3_M_AXI_BID <= M_AXI_BID ; 546 CH3_M_AXI_BRESP <= M_AXI_BRESP ; 547 CH3_M_AXI_BUSER <= M_AXI_BUSER ; 548 CH3_M_AXI_BVALID <= M_AXI_BVALID ; 549 M_AXI_BREADY <= CH3_M_AXI_BREADY ; 550 end else begin 551 M_AXI_AWID <= CH3_M_AXI_AWID ; 552 M_AXI_AWADDR <= CH3_M_AXI_AWADDR ; 553 M_AXI_AWLEN <= CH3_M_AXI_AWLEN ; 554 M_AXI_AWSIZE <= CH3_M_AXI_AWSIZE ; 555 M_AXI_AWBURST <= CH3_M_AXI_AWBURST; 556 M_AXI_AWLOCK <= CH3_M_AXI_AWLOCK ; 557 M_AXI_AWCACHE <= CH3_M_AXI_AWCACHE; 558 M_AXI_AWPROT <= CH3_M_AXI_AWPROT ; 559 M_AXI_AWQOS <= CH3_M_AXI_AWQOS ; 560 M_AXI_AWUSER <= CH3_M_AXI_AWUSER ; 561 M_AXI_AWVALID <= CH3_M_AXI_AWVALID; 562 CH3_M_AXI_AWREADY <= M_AXI_AWREADY ; 563 M_AXI_WDATA <= CH3_M_AXI_WDATA ; 564 M_AXI_WSTRB <= CH3_M_AXI_WSTRB ; 565 M_AXI_WLAST <= CH3_M_AXI_WLAST ; 566 M_AXI_WUSER <= CH3_M_AXI_WUSER ; 567 M_AXI_WVALID <= CH3_M_AXI_WVALID ; 568 CH3_M_AXI_WREADY <= M_AXI_WREADY ; 569 CH3_M_AXI_BID <= M_AXI_BID ; 570 CH3_M_AXI_BRESP <= M_AXI_BRESP ; 571 CH3_M_AXI_BUSER <= M_AXI_BUSER ; 572 CH3_M_AXI_BVALID <= M_AXI_BVALID ; 573 M_AXI_BREADY <= CH3_M_AXI_BREADY ; 574 end 575 end 576 endmodule
