摘要： //clK系统时钟为50MHZ 先发地位后发高位module uart_tx (input clk,rst_n,UART_CTS,output reg UART_RTS,output reg UART_RXD,output reg UART_TXD);reg [3:0]state;reg [30:0] count;reg [7:0] data;always @ (posedge clk)begin if(!rst_n) begin UART_TXD=0;data<=8'ha5;endelse begin case (state) 0:if(count==5208) begin s 阅读全文