最简易的RS232 建模一（发送）

//clK系统时钟为50MHZ 先发地位后发高位
module uart_tx (input clk,rst_n, UART_CTS,
 output reg UART_RTS,
 output reg UART_RXD,
 output reg UART_TXD);
reg [3:0]state;
reg [30:0] count;
reg [7:0] data;
always @ (posedge clk)
begin
if(!rst_n) begin UART_TXD=0;data<=8'ha5;end
else begin
 case (state)
    0:if(count==5208) begin state<=1;count<=0;end
    else            begin state<=0;count<=count+1;UART_TXD=0;      end //开始位
  1:if(count==5208) begin state<=2;count<=0;end
    else            begin state<=1;count<=count+1;UART_TXD=data[0];end  
  2:if(count==5208) begin state<=3;count<=0;end
    else            begin state<=2;count<=count+1;UART_TXD=data[1];end
  3:if(count==5208) begin state<=4;count<=0;end
    else            begin state<=3;count<=count+1;UART_TXD=data[2];end 
  4:if(count==5208) begin state<=5;count<=0;end
    else            begin state<=4;count<=count+1;UART_TXD=data[3];end 
  5:if(count==5208) begin state<=6;count<=0;end
    else            begin state<=5;count<=count+1;UART_TXD=data[4];end  
  6:if(count==5208) begin state<=7;count<=0;end
    else            begin state<=6;count<=count+1;UART_TXD=data[5];end
  7:if(count==5208) begin state<=8;count<=0;end
    else            begin state<=7;count<=count+1;UART_TXD=data[6];end 
  8:if(count==5208) begin state<=9;count<=0;end
    else            begin state<=8;count<=count+1;UART_TXD=data[7];end 
  9:if(count==5208) begin state<=10;count<=0;end
    else            begin state<=9;count<=count+1;UART_TXD=1;      end //结束位
  10:state=0;
  default state=0;
  endcase
end
end
endmodule