基于DE2 七段数码管IP设计

开发环境Quartus II 9.0 + NIOS II 9.0 + DE2

一、七段数码管IP

///////////////////////////////////////////////////////////////////////////////

module avalon_slave_SEG7(clock,reset_n,address,write,writedata,read,readdata,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7);
input   write,read,clock,reset_n,address;
input  [31:0] writedata;
output  [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;
output  reg  [31:0]  readdata;

reg  [31:0] data;

always@(posedge clock or negedge reset_n)
begin
 if(!reset_n) data <= 32'bzzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz;
 else
 begin
  if(write && (!address)) data <= writedata;
 end
end

always@(posedge clock or negedge reset_n)
begin
 if(!reset_n) readdata <= 32'bzzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz;
 else
 begin
  if(read && (!address)) readdata <= data;
 end
end

SEG7_LUT u0 ( HEX0,data[3:0]  );
SEG7_LUT u1 ( HEX1,data[7:4]  );
SEG7_LUT u2 ( HEX2,data[11:8]      );
SEG7_LUT u3 ( HEX3,data[15:12] );
SEG7_LUT u4 ( HEX4,data[19:16] ); 
SEG7_LUT u5 ( HEX5,data[23:20] );
SEG7_LUT u6 ( HEX6,data[27:24] );
SEG7_LUT u7 ( HEX7,data[31:28] );

endmodule

module SEG7_LUT ( HEX,data );
input [3:0] data;
output [6:0] HEX;
reg [6:0] HEX;

always @(data)
begin
 case(data)

  4'h0: HEX = 7'b1000000;
  4'h1: HEX = 7'b1111001;
  4'h2: HEX = 7'b0100100;
  4'h3: HEX = 7'b0110000;
  4'h4: HEX = 7'b0011001;
  4'h5: HEX = 7'b0010010;
  4'h6: HEX = 7'b0000010;
  4'h7: HEX = 7'b1111000;
  4'h8: HEX = 7'b0000000;
  4'h9: HEX = 7'b0011000;
  4'ha: HEX = 7'b0001000;
  4'hb: HEX = 7'b0000011;
  4'hc: HEX = 7'b1000110;
  4'hd: HEX = 7'b0100001;
  4'he: HEX = 7'b0000110;
  4'hf: HEX = 7'b0001110;

 endcase
end

endmodule

/////////////////////////////////////////////////////////////////

二、SOPC Building配置如图：

三、顶层工程文件

四、七段数码管头文件

#ifndef   __avalon_slave_SEG7_H__
#define   __avalon_slave_SEG7_H__

#include <io.h>
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include "system.h"
#include "sys/alt_irq.h"

//  for GPIO
#define inport(base)                                  IORD(base, 0)
//  for SEG7 Display
#define seg7_show(base,data)                          IOWR(base, 0, data)

void seg7(alt_u32 base,alt_u8 data,alt_u8 num)
{
    alt_u32 readdata,writedata;
    readdata = inport(base);
    writedata = (readdata & (~(0x0F<<4*num))) | (data<<4*num);
    seg7_show(base,writedata);
}

//  for Time Delay
#define msleep(msec)                                  usleep(1000*msec);
#define Sleep(sec)                                    msleep(1000*sec);

#endif

五、主程序

#include"system.h"
#include"avalon_slave_SEG7.h"

int main(void)
{
    unsigned char i;
    for(i=1;i<=8;i++)
    seg7(SEG7_BASE,i,i-1);
    return 0;
}