SystemVerilog学习三 —— Gray码

1、gray counter

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module gray(
output wire [7:0] out    , // counter out
input  wire       enable , // enable for counter
input  wire       clk    , // clock
input  wire       rst      // active hight reset
);
//------------Internal Variables--------
reg [7:0] count;
//-------------Code Starts Here---------
always_ff @ (posedge clk)
if (rst) begin
  count <= 0;
end else if (enable) begin
  count ++;
end
 
assign out = { count[7], (count[7] ^ count[6]),(count[6] ^
             count[5]),(count[5] ^ count[4]), (count[4] ^
             count[3]),(count[3] ^ count[2]), (count[2] ^
             count[1]),(count[1] ^ count[0]) };
 
endmodule

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2、gray counter 2

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`timescale 1ns/1ps
module GrayCounter
     #(parameter   COUNTER_WIDTH = 4)  (
     output reg  [COUNTER_WIDTH-1:0]    GrayCount_out,  //'Gray' code count output.
     input wire                         Enable_in,  //Count enable.
     input wire                         Clear_in,   //Count reset.
     input wire                         Clk);

    /////////Internal connections & variables///////
    reg    [COUNTER_WIDTH-1:0]         BinaryCount;

    /////////Code///////////////////////
  always@(posedge Clk)
        if (Clear_in) begin
            BinaryCount   <= '0 + 1'b1;  //Gray count begins @ '1' with
            GrayCount_out <= '0;      // first 'Enable_in'.
        end
        else if (Enable_in) begin
            BinaryCount ++;
            GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
                              BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
        end
   
endmodule

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