基于TLC549 ADC的FPGA测试代码设计

1、首先看看TLC549的电路图：

TLC549与FPGA只有三根信号线连接

2、下面为TLC549的时序图：

CS到第一个clk的建立时间为2个clk周期

3、TLC549的驱动代码：

module TLC549 ( 
                    input clk,
                    input reset,
                    input AD_DATA,
                    output AD_CS,
                    output AD_CLK,
                    output clk_display,
                    output reg [7:0] readdata                    
               );

// clk=50MHz , AD_CLK_r = 1MHz              
reg  AD_CLK_r;
reg[5:0] DCLK_DIV; 

always @(posedge clk or negedge reset)
begin
  if(!reset)
  begin
      DCLK_DIV <= 1'b0;
      AD_CLK_r <= 1'b0;
  end
  else if(DCLK_DIV < 6'd50) DCLK_DIV <= DCLK_DIV+1'b1;
  else
    begin
      DCLK_DIV <= 0;
      AD_CLK_r <= ~AD_CLK_r;
    end
 end
 
assign clk_display = AD_CLK_r;

reg[4:0] COUNTER;

always @(posedge AD_CLK_r or negedge reset)
begin
    if(!reset) COUNTER <= 1'b0;
    else COUNTER <= COUNTER+1'b1;
end

assign AD_CS = (COUNTER <= 5'd9)? 1'b0 : 1'b1;

assign AD_CLK =  (COUNTER >= 5'd2 && COUNTER <= 5'd9)? AD_CLK_r : 1'b0;

reg[7:0] data_reg;

always @(negedge AD_CLK_r)
begin
  if(COUNTER >= 5'd2 && COUNTER <= 5'd9)  
     begin
       data_reg[0] <= AD_DATA;
       data_reg[7:1] <= data_reg[6:0];
     end
  else  readdata <= data_reg; 
 end
 
endmodule

4、数码管显示代码：

module display(
                input clk,
                input[7:0] data,
                input reset,
                output reg [7:0] seg,
                output reg [3:0] com );
reg [14:0] cnt;

always@(posedge clk or negedge reset)
begin
   if(!reset) cnt <= 12'd0;
   else cnt <= cnt + 1'b1;
end

reg[7:0] seg_reg;

always@(cnt[11:10] or data)
begin
  case(cnt[11:10])
   2'b00 : begin com <= 4'b1110; seg_reg <= data%8'd10;      end
   2'b01 : begin com <= 4'b1101; seg_reg <= data%8'd100/8'd10;  end
   2'b10 : begin com <= 4'b1011; seg_reg <= data/8'd100;     end
   default : begin com <= 4'b1111;seg_reg <= 8'bzzzz_zzzz;end
  endcase
end

always @(com or seg_reg)
begin
 case(seg_reg[3:0])
  4'h0:seg=8'hc0; //显示0
  4'h1:seg=8'hf9; //显示1
  4'h2:seg=8'ha4; //显示2
  4'h3:seg=8'hb0; //显示3
  4'h4:seg=8'h99; //显示4
  4'h5:seg=8'h92; //显示5
  4'h6:seg=8'h82; //显示6
  4'h7:seg=8'hf8; //显示7
  4'h8:seg=8'h80; //显示8
  4'h9:seg=8'h90; //显示9
      default: seg=8'hff;
 endcase
end

endmodule

4、建立工程，例化上面两个模块，并完成原理图设计：

5、新建TCL脚本文件，锁定引脚：

set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF
set_location_assignment PIN_23 -to clk                               
set_location_assignment PIN_56 -to reset 

set_location_assignment PIN_137 -to com\[0\]
set_location_assignment PIN_135 -to com\[1\]
set_location_assignment PIN_139 -to com\[2\]
set_location_assignment PIN_138 -to com\[3\]

set_location_assignment PIN_133 -to seg\[0\]
set_location_assignment PIN_127 -to seg\[1\]
set_location_assignment PIN_116 -to seg\[2\]
set_location_assignment PIN_117 -to seg\[3\]
set_location_assignment PIN_128 -to seg\[4\]
set_location_assignment PIN_134 -to seg\[5\]
set_location_assignment PIN_115 -to seg\[6\]
set_location_assignment PIN_118 -to seg\[7\]

set_location_assignment PIN_89 -to ad_clk
set_location_assignment PIN_105 -to ad_cs
set_location_assignment PIN_90 -to ad_data