HDLBits
Verilog Language
Basics
7458
module top_module ( input p1a, p1b, p1c, p1d, p1e, p1f, output p1y, input p2a, p2b, p2c, p2d, output p2y ); assign p1y = (p1a & p1b & p1c) | (p1d & p1e & p1f); assign p2y = (p2a & p2b) | (p2c & p2d); endmodule
Vectors
Vectors
module top_module ( input wire [2:0] vec, output wire [2:0] outv, output wire o2, output wire o1, output wire o0 ); // Module body starts after module declaration assign outv = vec; assign {o2, o1, o0} = vec; endmodule
Vectors in more detail
`default_nettype none // Disable implicit nets. Reduces some types of bugs. module top_module( input wire [15:0] in, output wire [7:0] out_hi, output wire [7:0] out_lo ); assign {out_hi, out_lo} = in; endmodule
Vector part select
module top_module( input [31:0] in, output [31:0] out );// assign {out[7:0], out[15:8], out[23:16], out[31:24]} = in; endmodule
Bitwise operators
module top_module( input [2:0] a, input [2:0] b, output [2:0] out_or_bitwise, output out_or_logical, output [5:0] out_not ); assign out_or_bitwise = a | b; assign out_or_logical = a || b; assign out_not = {~b,~a}; endmodule
4-input gates
module top_module( input [3:0] in, output out_and, output out_or, output out_xor ); assign out_and= ∈ assign out_or= |in; assign out_xor= ^in; endmodule
Vector concatenation operator
module top_module ( input [4:0] a, b, c, d, e, f, output [7:0] w, x, y, z );// assign {w, x, y, z} = {a, b, c, d, e, f, 2'b11}; endmodule
Vector reversal1
module top_module( input [7:0] in, output [7:0] out ); assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]}; endmodule
注意：声明in[7:0]后，语法不允许使用in[0:7]。
Replication operator
module top_module ( input [7:0] in, output [31:0] out );// assign out = {{24{in[7]}}, in}; endmodule
注意：{24{in[7]}}外面这层括号不能去掉。
More replication
module top_module ( input a, b, c, d, e, output [24:0] out );// assign out = {{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}} ^~ {5{a, b, c, d, e}}; endmodule
Module: Hierarchy
Modules
module top_module ( input a, input b, output out ); mod_a instance1(a, b, out); endmodule
Connecting ports by position
module top_module ( input a, input b, input c, input d, output out1, output out2 ); mod_a instance1(out1, out2, a, b, c, d ); endmodule
Connecting ports by name
module top_module ( input a, input b, input c, input d, output out1, output out2 ); mod_a instance1(.out1(out1), .out2(out2), .in1(a), .in2(b), .in3(c), .in4(d)); endmodule
Three modules
module top_module ( input clk, input d, output q ); reg q1, q2; my_dff instance1(clk, d, q1); my_dff instance2(clk, q1, q2); my_dff instance3(clk, q2, q); endmodule
Modules and vectors
module top_module ( input clk, input [7:0] d, input [1:0] sel, output [7:0] q ); reg[7:0] q1, q2, q3; my_dff8 instance1(clk, d, q1); my_dff8 instance2(clk, q1, q2); my_dff8 instance3(clk, q2, q3); always @(*) begin case (sel) 2'b00: q = d; 2'b01: q = q1; 2'b10: q = q2; 2'b11: q = q3; default: q = d; endcase end endmodule
Adder1
module top_module( input [31:0] a, input [31:0] b, output [31:0] sum ); reg cout; add16 addlo(a[15:0], b[15:0], 0, sum[15:0], cout); add16 addhi(a[31:16], b[31:16], cout, sum[31:16], 0); endmodule
Adder2
module top_module ( input [31:0] a, input [31:0] b, output [31:0] sum );// reg cout; add16 addlo(a[15:0], b[15:0], 0, sum[15:0], cout); add16 addhi(a[31:16], b[31:16], cout, sum[31:16], 0); endmodule module add1 ( input a, input b, input cin, output sum, output cout ); assign sum = a ^ b ^ cin; assign cout = a&b | a&cin | b&cin; endmodule /* module add16 ( input [15:0] a, input [15:0] b, input cin, output [15:0] sum, output cout ); wire [14:0] cout_tmp; add1 inst01(a[0], b[0], 0, sum[0], cout_tmp[0]); add1 inst02(a[1], b[1], cout_tmp[0], sum[1], cout_tmp[1]); add1 inst03(a[2], b[2], cout_tmp[1], sum[2], cout_tmp[2]); add1 inst04(a[3], b[3], cout_tmp[2], sum[3], cout_tmp[3]); add1 inst05(a[4], b[4], cout_tmp[3], sum[4], cout_tmp[4]); add1 inst06(a[5], b[5], cout_tmp[4], sum[5], cout_tmp[5]); add1 inst07(a[6], b[6], cout_tmp[5], sum[6], cout_tmp[6]); add1 inst08(a[7], b[7], cout_tmp[6], sum[7], cout_tmp[7]); add1 inst09(a[8], b[8], cout_tmp[7], sum[8], cout_tmp[8]); add1 inst10(a[9], b[9], cout_tmp[8], sum[9], cout_tmp[9]); add1 inst11(a[10], b[10], cout_tmp[9], sum[10], cout_tmp[10]); add1 inst12(a[11], b[11], cout_tmp[10], sum[11], cout_tmp[11]); add1 inst13(a[12], b[12], cout_tmp[11], sum[12], cout_tmp[12]); add1 inst14(a[13], b[13], cout_tmp[12], sum[13], cout_tmp[13]); add1 inst15(a[14], b[14], cout_tmp[13], sum[14], cout_tmp[14]); add1 inst16(a[15], b[15], cout_tmp[14], sum[15], cout); endmodule */
Carry-select adder
module top_module( input [31:0] a, input [31:0] b, output [31:0] sum ); wire sel; wire [15:0] sum0, sum1; add16 instance1(a[15:0], b[15:0], 0, sum[15:0], sel); add16 instance2(a[31:16], b[31:16], 0, sum0[15:0]); add16 instance3(a[31:16], b[31:16], 1, sum1[15:0]); assign sum[31:16] = sel ? sum1[15:0] : sum0[15:0]; endmodule
Adder-subtractor
module top_module( input [31:0] a, input [31:0] b, input sub, output [31:0] sum ); reg cout; add16 instance1(a[15:0], b[15:0]^{16{sub}}, sub, sum[15:0], cout); add16 instance2(a[31:16], b[31:16]^{16{sub}}, cout, sum[31:16]); endmodule
Procedures
Always Blocks（Combinational）
// synthesis verilog_input_version verilog_2001 module top_module( input a, input b, output wire out_assign, output reg out_alwaysblock ); assign out_assign = a & b; always @(a,b) begin out_alwaysblock = a & b; end endmodule
Always Blocks（Clocked）
// synthesis verilog_input_version verilog_2001 module top_module( input clk, input a, input b, output wire out_assign, output reg out_always_comb, output reg out_always_ff ); assign out_assign = a ^ b; always @(*) begin out_always_comb = a ^ b; end always @(posedge clk) begin out_always_ff = a ^ b; end endmodule
If statement
// synthesis verilog_input_version verilog_2001 module top_module( input a, input b, input sel_b1, input sel_b2, output wire out_assign, output reg out_always ); assign out_assign = (sel_b1 && sel_b2) ? b : a; always @(*) begin if (sel_b1 && sel_b2) out_always = b; else out_always = a; end endmodule
If statement latches
// synthesis verilog_input_version verilog_2001 module top_module ( input cpu_overheated, output reg shut_off_computer, input arrived, input gas_tank_empty, output reg keep_driving ); // always @(*) begin if (cpu_overheated) shut_off_computer = 1; else shut_off_computer = 0; end always @(*) begin if (~arrived) keep_driving = ~gas_tank_empty; else keep_driving = 0; end endmodule
Case statement
// synthesis verilog_input_version verilog_2001 module top_module ( input [2:0] sel, input [3:0] data0, input [3:0] data1, input [3:0] data2, input [3:0] data3, input [3:0] data4, input [3:0] data5, output reg [3:0] out );// always@(*) begin // This is a combinational circuit case(sel) 0: out = data0; 1: out = data1; 2: out = data2; 3: out = data3; 4: out = data4; 5: out = data5; default: out = 0; endcase end endmodule
Priority encoder
// synthesis verilog_input_version verilog_2001 module top_module ( input [3:0] in, output reg [1:0] pos ); always @(*) begin case (in) 0,1,3,5,7,9,11,13,15: pos = 0; 2,6,10,14: pos = 1; 4,12: pos = 2; 8: pos = 3; default: pos = 0; endcase end endmodule
Priority encoder with casez
// synthesis verilog_input_version verilog_2001 module top_module ( input [7:0] in, output reg [2:0] pos ); always @(*) begin casez (in[7:0]) 8'bzzzzzzz1: pos = 0; 8'bzzzzzz1z: pos = 1; 8'bzzzzz1zz: pos = 2; 8'bzzzz1zzz: pos = 3; 8'bzzz1zzzz: pos = 4; 8'bzz1zzzzz: pos = 5; 8'bz1zzzzzz: pos = 6; 8'b1zzzzzzz: pos = 7; default: pos = 0; endcase end endmodule
备注：casez中z对应的任何输入都判定为真。
Avoiding latches
// synthesis verilog_input_version verilog_2001 module top_module ( input [15:0] scancode, output reg left, output reg down, output reg right, output reg up ); always @(*) begin case (scancode[15:0]) 16'he06b: {left, down, right, up} = 4'b1000; 16'he072: {left, down, right, up} = 4'b0100; 16'he074: {left, down, right, up} = 4'b0010; 16'he075: {left, down, right, up} = 4'b0001; default: {left, down, right, up} = 4'b0000; endcase end endmodule
More verilog features
Conditional ternary operator（条件三元操作符）
module top_module ( input [7:0] a, b, c, d, output [7:0] min);// wire [7:0] intermediate_result1, intermediate_result2; assign intermediate_result1 = a < b? a: b; assign intermediate_result2 = intermediate_result1 < c? intermediate_result1: c; assign min = intermediate_result2 < d? intermediate_result2: d; endmodule
Reduction operators（缩减运算符）
module top_module ( input [7:0] in, output parity); assign parity = ^in; endmodule
Reduction:Even wider gates
module top_module( input [99:0] in, output out_and, output out_or, output out_xor ); assign out_and = ∈ assign out_or = |in; assign out_xor = ^in; endmodule
Combinational for-loop: Vector reversal 2
module top_module( input [99:0] in, output [99:0] out ); parameter num = 100; wire [7:0] i; always @(*) for (i = 0; i < num; i++) out[i] = in[num - 1 - i]; endmodule
Combinational for-loop: 255-bit population counter
module top_module( input [254:0] in, output [7:0] out ); parameter num = 255; wire [7:0] i; always @(*) begin out = 8'b00000000; for (i = 0; i < num; i++) if (in[i]) out = out + 1'b1; end endmodule
Generate for-loop: 100-bit binary adder 2
module top_module( input [99:0] a, b, input cin, output [99:0] cout, output [99:0] sum ); parameter num = 100; wire [6:0] i; wire tmp; always @(*) begin for (i = 0; i < num; i++) begin tmp = i==0 ? cin : cout[i-1]; {cout[i], sum[i]} = a[i] + b[i] + tmp; end end endmodule
Generate for-loop: 100-bit digital BCD adder
module top_module( input [399:0] a, b, input cin, output cout, output [399:0] sum ); wire [99:0] cc; bcd_fadd bcd_fadd_inst( .a (a[3:0]), .b (b[3:0]), .cin (cin) , .cout (cc[0]) , .sum (sum[3:0]) ); //由generate生成的模块 generate genvar i; for (i=1;i<100;++i) begin: bcd_fadd1 bcd_fadd bcd_fadd_inst( .a (a[(7+4*(i-1)):(4+4*(i-1))]), .b (b[(7+4*(i-1)):(4+4*(i-1))]), .cin (cc[i-1]), .cout (cc[i]), .sum (sum[(7+4*(i-1)):(4+4*(i-1))]) ); end endgenerate assign cout = cc[99]; endmodule
Ciruits
Combinational logic
Multiplexer
2-to-1 multiplexer
module top_module( input a, b, sel, output out ); assign out = sel ? b : a; endmodule
2-to-1 bus multiplexer
module top_module( input [99:0] a, b, input sel, output [99:0] out ); assign out = sel ? b : a; endmodule
9-to-1 multiplexer
module top_module( input [15:0] a, b, c, d, e, f, g, h, i, input [3:0] sel, output [15:0] out ); always @(*) begin case (sel) 0: out = a; 1: out = b; 2: out = c; 3: out = d; 4: out = e; 5: out = f; 6: out = g; 7: out = h; 8: out = i; default: out = 16'hffff; endcase end endmodule
256-to-1 multiplexer
module top_module( input [255:0] in, input [7:0] sel, output out ); assign out = in[sel]; endmodule
256-to-1 4-bit multiplexer
module top_module( input [1023:0] in, input [7:0] sel, output [3:0] out ); assign out = {in[4*sel+3],in[4*sel+2],in[4*sel+1],in[4*sel+0]}; endmodule
备注：assign out = in[4*sel+3:4*sel];不可行。
Arithmetic circuits
Half adder
module top_module( input a, b, output cout, sum ); assign {cout, sum} = a + b; endmodule
Full adder
module top_module( input a, b, cin, output cout, sum ); assign {cout, sum} = a + b + cin; endmodule
Adder
module top_module ( input [3:0] x, input [3:0] y, output [4:0] sum); assign sum = x + y; endmodule
Signed addtion overflow
module top_module ( input [7:0] a, input [7:0] b, output [7:0] s, output overflow ); // assign s = a + b; assign overflow = (a[7] & b[7] & !s[7]) | (!a[7] & !b[7] & s[7]); endmodule
100-bit binary adder
module top_module( input [99:0] a, b, input cin, output cout, output [99:0] sum ); assign {cout, sum} = a + b + cin; endmodule
4-BCD digital adder
module top_module ( input [15:0] a, b, input cin, output cout, output [15:0] sum ); wire [2:0] cc; bcd_fadd bcd_fadd_inst1( .a (a[3:0]), .b (b[3:0]), .cin (cin) , .cout (cc[0]) , .sum (sum[3:0]) ); bcd_fadd bcd_fadd_inst2( .a (a[7:4]), .b (b[7:4]), .cin (cc[0]) , .cout (cc[1]) , .sum (sum[7:4]) ); bcd_fadd bcd_fadd_inst3( .a (a[11:8]), .b (b[11:8]), .cin (cc[1]) , .cout (cc[2]) , .sum (sum[11:8]) ); bcd_fadd bcd_fadd_inst4( .a (a[15:12]), .b (b[15:12]), .cin (cc[2]) , .cout (cout) , .sum (sum[15:12]) ); endmodule
Karnaugh map to circuits（待补）
3-variable
module top_module( input a, input b, input c, output out ); assign out = a|b|c; endmodule
Sequential logic
Latches and Flip-flops
D-flip-flop
module top_module ( input clk, // Clocks are used in sequential circuits input d, output reg q );// always @ (posedge clk) q <= d; endmodule
备注：题目为什么要求使用非阻塞赋值？组合逻辑（combination logic）用阻塞赋值，时序逻辑（sequential logic）用非阻塞赋值。
D-flip-flops
module top_module ( input clk, input [7:0] d, output [7:0] q ); always @ (posedge clk) q <= d; endmodule
DFF with reset
module top_module ( input clk, input reset, // Synchronous reset input [7:0] d, output [7:0] q ); always @ (posedge clk) begin if (reset) q <= 8'b0; else q <= d; end endmodule
DFF with reset value
module top_module ( input clk, input reset, input [7:0] d, output [7:0] q ); always @ (negedge clk) begin if (reset) q <= 8'h34; else q <= d; end endmodule
DFF with asynchronous reset
module top_module ( input clk, input areset, // active high asynchronous reset input [7:0] d, output [7:0] q ); always @ (posedge clk or posedge areset) if (areset) q <= 8'h00; else q <= d; endmodule
DFF with byte enable
module top_module ( input clk, input resetn, input [1:0] byteena, input [15:0] d, output [15:0] q ); always @ (posedge clk) begin if (!resetn) q <= 16'h0000;
else
begin
if (byteena[1]) q[15:8] <= d[15:8];
if (byteena[0]) q[7:0] <= d[7:0];
end
end
endmodule
D Latch
module top_module ( input d, input ena, output q); always @ (ena or d) if (ena) q <= d; endmodule
DFF
module top_module ( input clk, input d, input ar, // asynchronous reset output q); always @ (posedge clk or posedge ar) if (ar) q <= 1'b0; else q <= d; endmodule
DFF
module top_module ( input clk, input d, input r, // synchronous reset output q); always @ (posedge clk) begin if (r) q <= 1'b0; else q <= d; end endmodule
DFF + gate
module top_module ( input clk, input in, output out); always @ (posedge clk) out <= in ^ out; endmodule
MUX and DFF
module top_module ( input clk, input L, input r_in, input q_in, output reg Q); always @ (posedge clk) Q <= L ? r_in : q_in; endmodule
MUX and DFF
module top_module ( input clk, input w, R, E, L, output Q ); always @ (posedge clk) Q = L ? R : E ? w : Q; endmodule
DFFs and gates
module top_module ( input clk, input x, output z ); reg q1, q2, q3; assign z = !(q1 | q2 | q3); always @ (posedge clk) begin q1 <= x ^ q1; q2 <= x & !q2; q3 <= x | !q3; end endmodule
Create ciruit from truth table
module top_module ( input clk, input j, input k, output Q); always @ (posedge clk) begin case ({j,k}) 2'b00: Q = Q; 2'b01: Q = 0; 2'b10: Q = 1; 2'b11: Q = ~Q; endcase end endmodule
Detect an edge
module top_module ( input clk, input [7:0] in, output [7:0] pedge ); reg [7:0] tmp; always @ (posedge clk) begin tmp <= in; pedge <= in & (~tmp); end endmodule
Detect both edge
module top_module ( input clk, input [7:0] in, output [7:0] anyedge ); reg [7:0] tmp; always @ (posedge clk) begin tmp <= in; anyedge <= in ^ tmp; end endmodule
Edge capture register
module top_module ( input clk, input reset, input [31:0] in, output [31:0] out ); reg [31:0] in1; always @ (posedge clk) begin in1 <= in; if (reset) out <= 0; else out <= ~in & in1 | out; end endmodule
Dual-edge reiggered flip-flop
module top_module ( input clk, input d, output q ); wire q1,q2; always@(posedge clk) q1 <= d; always@(negedge clk) q2 <= d; assign q = clk ? q1 : q2; endmodule
备注：FPGAs don't have dual-edge triggered flip-flops, and always @(posedge clk or negedge clk) is not accepted as a legal sensitivity list.以下是错误代码！
module top_module ( input clk, input d, output q ); always @ (posedge clk) q <= d; always @ (negedge clk) q <= d; endmodule
Counters
Four-bit binary counter
module top_module ( input clk, input reset, // Synchronous active-high reset output [3:0] q); always @ (posedge clk) begin if (reset) q <= 4'h0; else q <= q + 4'h1; end endmodule
Decade counter
module top_module( input clk, input reset, output reg [3:0] q); always @(posedge clk) if (reset || q == 9) // Count to 10 requires rolling over 9->0 instead of the more natural 15->0 q <= 0; else q <= q+1; endmodule
Decade counter again
module top_module ( input clk, input reset, output [3:0] q); always @(posedge clk) if (reset || q == 10) // Count to 10 requires rolling over 10->1 instead of the more natural 15->0 q <= 1; else q <= q+1; endmodule
Slow decade counter
module top_module ( input clk, input slowena, input reset, output [3:0] q); always @(posedge clk) if (reset) q <= 4'h0; else if (q == 4'h9 && slowena == 1'b1) q <= 4'h0; else if (slowena == 1'b1) q <= q + 4'h1; endmodule
Counter 1-12
module top_module ( input clk, input reset, input enable, output [3:0] Q, output c_enable, output c_load, output [3:0] c_d ); // assign c_enable = enable; assign c_load = reset | ((Q == 4'd12) && enable == 1'b1); //assign c_d = c_load ? 4'd1 : 4'd0; assign c_d = 4'd1; count4 count4_inst(clk, c_enable, c_load, c_d, Q); endmodule
Counter 1000
module top_module ( input clk, input reset, output OneHertz, output [2:0] c_enable ); // reg [3:0] Q1, Q2, Q3; assign c_enable[0] = 1'b1; assign c_enable[1] = Q1 == 4'd9; assign c_enable[2] = Q2 == 4'd9 && Q1 == 4'd9; assign OneHertz = Q3 == 4'd9 && Q2 == 4'd9 && Q1 == 4'd9; bcdcount counter0 (clk, reset, c_enable[0], Q1); bcdcount counter1 (clk, reset, c_enable[1], Q2); bcdcount counter2 (clk, reset, c_enable[2], Q3); endmodule
4-digital decimal counter（Countbcd）
查看代码
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output [15:0] q);
counter10 countbcd3(clk,ena[3],reset,q[15:12]);
counter10 countbcd2(clk,ena[2],reset,q[11:8]);
counter10 countbcd1(clk,ena[1],reset,q[7:4]);
counter10 countbcd0(clk,1,reset,q[3:0]);
assign ena[3] = (q[11:8] == 4'h9) && (q[7:4] == 4'h9) && (q[3:0] == 4'h9);
assign ena[2] = (q[7:4] == 4'h9) && (q[3:0] == 4'h9);
assign ena[1] = (q[3:0] == 4'h9);
endmodule
module counter10 (
input clk,
input en,
input reset,
output [3:0] q);
always @(posedge clk) begin
if (reset)
begin
q <= 0;
end
else
if (en)
begin
if (q == 4'h9) q <= 4'h0;
else q <= q + 1;
end
end
endmodule
12-hour clock（Count clock）
查看代码
module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
wire hh_ena, mm_ena;
counterhh countbcdhh(clk,hh_ena,reset,hh[7:0]);
countermm countbcdmm(clk,mm_ena,reset,mm[7:0]);
countermm countbcdss(clk,ena,reset,ss[7:0]);
assign hh_ena = (mm == 8'h59 && ss == 8'h59);
assign mm_ena = (ss == 8'h59);
always @(posedge clk) begin
if(reset) pm <= 0;
else begin
if (ena)
if(hh == 8'h11 && mm == 8'h59 && ss == 8'h59) pm <= ~pm;
end
end
endmodule
module countermm (
input clk,
input en,
input reset,
output [7:0] q);
always @(posedge clk) begin
if (reset)
begin
q <= 0;
end
else
if (en)
begin
if (q == 8'h59) q <= 8'h00;
else if (q[3:0] == 4'h9) begin
q[7:4] <= q[7:4] + 4'h01;
q[3:0] <= 4'h0;
end
else q <= q + 8'h01;
end
end
endmodule
module counterhh (
input clk,
input en,
input reset,
output [7:0] q);
always @(posedge clk) begin
if (reset)
begin
q <= 8'h12;
end
else
if (en)
begin
if (q == 8'h12) q <= 8'h01;
else if (q[3:0] == 4'h9) begin
q[7:4] <= q[7:4] + 4'h01;
q[3:0] <= 4'h0;
end
else q <= q + 8'h01;
end
end
endmodule
Shift Registers
4-bit shift register（Shift4）
查看代码
module top_module(
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q);
always @(posedge clk or posedge areset) begin
if(areset) q <= 4'h0;
else begin
if(load) q <= data;
else if(ena) q[3:0] <= {1'b0,q[3:1]};
end
end
endmodule
Left/right rotator（Rotate100）
查看代码
module top_module(
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q);
always @(posedge clk) begin
if(load) q <= data;
else begin
case(ena[1:0])
2'b01: q <= {q[0], q[99:1]};
2'b10: q <= {q[98:0],q[99]};
//default:
endcase
end
end
endmodule
Left/right arithmatic shift by 1 or 8（shift18）
查看代码
module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
always @(posedge clk) begin
if(load) q <= data;
else begin
if(ena) begin
case(amount)
2'b00: q <= {q[62:0], 1'b0};
2'b01: q <= {q[55:0], 8'h00};
2'b10: q <= {{2{q[63]}}, q[62:1]};
2'b11: q <= {{9{q[63]}}, q[62:8]};
endcase
end
end
end
endmodule
5-bit LFSR（lfsr5）
查看代码
module top_module(
input clk,
input reset, // Active-high synchronous reset to 5'h1
output [4:0] q
);
always @(posedge clk) begin
if(reset) q <= 5'h1;
else begin
q[4] <= q[0] ^ 1'b0;
q[3] <= q[4];
q[2] <= q[0] ^ q[3];
q[1] <= q[2];
q[0] <= q[1];
end
end
endmodule
3-bit LFSR（Mt2015 lfsr）
查看代码
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output [2:0] LEDR); // Q
lfsr_3_bit u1(.R(SW), .clk(KEY[0]), .L(KEY[1]), .Q(LEDR));
endmodule
module lfsr_3_bit(
input [2:0] R,
input clk,
input L,
output [2:0] Q);
always @(posedge clk) begin
if(L) Q <= R;
else begin
Q[0] <= Q[2];
Q[1] <= Q[0];
Q[2] <= Q[1] ^ Q[2];
end
end
endmodule
32-bit LFSR（lfsr32）
查看代码
// 参考5 bit LFSR问题中的图
module top_module(
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
always @(posedge clk) begin
if(reset) q <= 32'h0000_0001;
else begin
q[31] <= 1'b0 ^ q[0];
q[30:22] <= q[31:23];
q[21] <= q[22] ^ q[0];
q[20:2] <= q[21:3];
q[1] <= q[2] ^ q[0];
q[0] <= q[1] ^ q[0];
end
end
endmodule
Shift register（Exams/m2014 q4k）
查看代码
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out);
reg [3:0] q;
assign out = q[3];
always @(posedge clk) begin
if(!resetn) q <= 4'h0;
else q <= {q[2:0], in};
end
endmodule
Shift register（Exams/2014 q4b）
查看代码
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
); //
MUXDFF u0(.clk(KEY[0]), .L(KEY[2]), .R(SW[3]), .E(KEY[1]), .din(KEY[3]), .dout(LEDR[3]));
MUXDFF u1(.clk(KEY[0]), .L(KEY[2]), .R(SW[2]), .E(KEY[1]), .din(LEDR[3]), .dout(LEDR[2]));
MUXDFF u2(.clk(KEY[0]), .L(KEY[2]), .R(SW[1]), .E(KEY[1]), .din(LEDR[2]), .dout(LEDR[1]));
MUXDFF u3(.clk(KEY[0]), .L(KEY[2]), .R(SW[0]), .E(KEY[1]), .din(LEDR[1]), .dout(LEDR[0]));
endmodule
module MUXDFF (
input clk,
input L,
input R,
input E,
input din,
output dout);
always @(posedge clk) begin
if(L) dout <= R;
else if(E) dout <= din;
end
endmodule
3-input LUT（Exams/ece241 2013 q12）
查看代码
module top_module (
input clk,
input enable,
input S,
input A, B, C,
output Z );
reg [7:0] q;
always @(posedge clk) begin
if(enable) q <= {q[6:0], S};
end
assign Z = q[{A,B,C}];
endmodule
More Circuits
Rule 90
查看代码
module top_module(
input clk,
input load,
input [511:0] data,
output [511:0] q );
always @(posedge clk) begin
if(load) q <= data;
else begin
integer i;
q[0] <= q[1];
q[511] <= q[510];
for(i=1;i<511;i++) begin
q[i] <= q[i+1] ^ q[i-1];
end
end
end
endmodule
Rule 110
查看代码
// B' = !A & (B | C) | B ^ C
module top_module(
input clk,
input load,
input [511:0] data,
output [511:0] q );
always @(posedge clk) begin
if(load) q <= data;
else begin
integer i;
q[0] <= !q[1]&(q[0]) | q[0];
q[511] <= (q[511]|q[510]) | q[511] ^ q[510];
for(i=1;i<511;i++) begin
q[i] <= !q[i+1]&(q[i]|q[i-1]) | q[i] ^ q[i-1];
end
end
end
endmodule
Conway's Game of Life 16X16(Conwaylife)
查看代码
module top_module(
input clk,
input load,
input [255:0] data,
output [255:0] q );
always @(posedge clk) begin
if(load) q <= data;
else begin
integer i, j;
for(i=0;i<16;i++) begin
for(j=0;j<16;j++) begin
case(q[16*((i-1+16)%16)+((j-1+16)%16)] + q[16*((i-1+16)%16)+((j+16)%16)] + q[16*((i-1+16)%16)+((j+1+16)%16)]
+ q[16*((i+16)%16)+((j-1+16)%16)] + q[16*((i+16)%16)+((j+1+16)%16)]
+ q[16*((i+1+16)%16)+((j-1+16)%16)] + q[16*((i+1+16)%16)+((j+16)%16)] + q[16*((i+1+16)%16)+((j+1+16)%16)])
3: q[16*i+j] <= 1;
2: q[16*i+j] <= q[16*i+j];
default: q[16*i+j] <= 0;
endcase
end
end
end
end
endmodule
Finite State Machines
simple FSM1, asynchronous reset(Fsm1)
查看代码
module top_module(
input clk,
input areset, // Asynchronous reset to state B
input in,
output out);//
parameter A=1'b0, B=1'b1;
reg state, next_state;
always @(*) begin // This is a combinational always block
// State transition logic
next_state <= in ? state : !state;
end
always @(posedge clk, posedge areset) begin // This is a sequential always block
// State flip-flops with asynchronous reset
if(areset) state <= B;
else state <= next_state;
end
// Output logic
// assign out = (state == ...);
assign out = (state == B);
endmodule
simple FSM1, synchronous reset(Fsm1s)
查看代码
// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out;
// Fill in state name declarations
parameter A = 1'b1, B = 1'b0;
reg present_state, next_state;
always @(posedge clk) begin
if (reset) begin
// Fill in reset logic
present_state = B;
out = 1'b1;
end else begin
case (present_state)
// Fill in state transition logic
A: next_state = in ? A : B;
B: next_state = in ? B : A;
// default: next_state = A;
endcase
// State flip-flops
present_state = next_state;
case (present_state)
// Fill in output logic
B: out = 1'b1;
A: out = 1'b0;
endcase
end
end
endmodule
simple FSM2, asynchronous reset(Fsm2)
查看代码
module top_module(
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
state = next_state;
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if(areset) begin
next_state <= OFF;
end
else begin
case(state)
OFF: next_state <= j ? ON : OFF;
ON: next_state <= k ? OFF : ON;
endcase
end
end
// Output logic
// assign out = (state == ...);
assign out = (state == ON);
endmodule
simple FSM2, synchronous reset(Fsm2s)
查看代码
module top_module(
input clk,
input reset, // Synchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
state = next_state;
end
always @(posedge clk) begin
// State flip-flops with synchronous reset
if(reset) next_state <= OFF;
else begin
case(state)
ON: next_state <= k ? OFF : ON;
OFF: next_state <= j ? ON : OFF;
endcase
end
end
// Output logic
// assign out = (state == ...);
assign out = (state == ON);
endmodule
simple state transitions 3(Fsm3comb)
查看代码
module top_module(
input in,
input [1:0] state,
output [1:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
// State transition logic: next_state = f(state, in)
always @(*) begin
case(state)
A: next_state = in ? B : A;
B: next_state = in ? B : C;
C: next_state = in ? D : A;
D: next_state = in ? B : C;
endcase
end
// Output logic: out = f(state) for a Moore state machine
assign out = (state == D);
endmodule
simple one-hot state transitions 3(Fsm3onehot)
查看代码
module top_module(
input in,
input [3:0] state,
output [3:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = state[A]&(~in) | state[C]&(~in);
assign next_state[B] = state[A]&(in) | state[B]&(in) | state[D]&(in);
assign next_state[C] = state[B]&(~in) | state[D]&(~in);
assign next_state[D] = state[C]&(in);
// Output logic:
assign out = (state[D] == 1'b1);
endmodule
simple FSM 3, asynchronous reset(Fsm3)
查看代码
module top_module(
input clk,
input in,
input areset,
output out); //
parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;
reg [1:0] state;
reg [1:0] next_state;
// State transition logic
always @(*) begin
state <= next_state;
end
// State flip-flops with asynchronous reset
always @(posedge clk or posedge areset) begin
if(areset) next_state <= A;
else begin
case(state)
A: next_state <= in ? B : A;
B: next_state <= in ? B : C;
C: next_state <= in ? D : A;
D: next_state <= in ? B : C;
endcase
end
end
// Output logic
assign out = state == D;
endmodule
simple FSM 3, synchronous reset(Fsm3s)
查看代码
module top_module(
input clk,
input in,
input reset,
output out); //
parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;
reg [2:0] state, next_state;
// State transition logic
always @(*) begin
state = next_state;
end
// State flip-flops with synchronous reset
always @(posedge clk) begin
if(reset) next_state <= A;
else begin
case(state)
A: next_state <= in ? B : A;
B: next_state <= in ? B : C;
C: next_state <= in ? D : A;
D: next_state <= in ? B : C;
endcase
end
end
// Output logic
assign out = (state == D);
endmodule
Design a Moore FSM(Exams/ece241 2013 q4)
查看代码
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
parameter A = 4'b1111, B1 = 4'b0111, B0 = 4'b0110, C1 = 4'b0011, C0 = 4'b0010, D = 4'b0000;
reg [3:0] state, next_state;
always @(*) begin
state = next_state;
end
always @(posedge clk) begin
if(reset) begin
next_state <= A;
end
else begin
case(s)
3'b000: next_state <= A;
3'b001: next_state <= (state < 4'b0100) ? B1 : (state == 4'b1111) ? B0 : state;
3'b011: next_state <= (state > 4'b0100) ? C0 : (state == 4'b0000) ? C1 : state;
3'b111: next_state <= D;
default: next_state <= A;
endcase
end
end
assign {fr3, fr2, fr1, dfr} = state;
endmodule官网参考答案
module top_module (
input clk,
input reset,
input [3:1] s,
output reg fr3,
output reg fr2,
output reg fr1,
output reg dfr
);
// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
// It doesn't really matter what assignment is used, as long as they're unique.
// We have 6 states here.
parameter A2=0, B1=1, B2=2, C1=3, C2=4, D1=5;
reg [2:0] state, next; // Make sure these are big enough to hold the state encodings.
// Edge-triggered always block (DFFs) for state flip-flops. Synchronous reset.
always @(posedge clk) begin
if (reset) state <= A2;
else state <= next;
end
// Combinational always block for state transition logic. Given the current state and inputs,
// what should be next state be?
// Combinational always block: Use blocking assignments.
always@(*) begin
case (state)
A2: next = s[1] ? B1 : A2;
B1: next = s[2] ? C1 : (s[1] ? B1 : A2);
B2: next = s[2] ? C1 : (s[1] ? B2 : A2);
C1: next = s[3] ? D1 : (s[2] ? C1 : B2);
C2: next = s[3] ? D1 : (s[2] ? C2 : B2);
D1: next = s[3] ? D1 : C2;
default: next = 'x;
endcase
end
// Combinational output logic. In this problem, a procedural block (combinational always block)
// is more convenient. Be careful not to create a latch.
always@(*) begin
case (state)
A2: {fr3, fr2, fr1, dfr} = 4'b1111;
B1: {fr3, fr2, fr1, dfr} = 4'b0110;
B2: {fr3, fr2, fr1, dfr} = 4'b0111;
C1: {fr3, fr2, fr1, dfr} = 4'b0010;
C2: {fr3, fr2, fr1, dfr} = 4'b0011;
D1: {fr3, fr2, fr1, dfr} = 4'b0000;
default: {fr3, fr2, fr1, dfr} = 'x;
endcase
end
endmodule
Lemmings1
查看代码
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
output walk_left,
output walk_right); //
parameter LEFT=0, RIGHT=1;
reg state, next_state;
always @(*) begin
// State transition logic
state = next_state;
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if(areset) next_state <= LEFT;
else begin
case({bump_right, bump_left})
2'b00: next_state <= state;
2'b01: next_state <= RIGHT;
2'b10: next_state <= LEFT;
2'b11: next_state <= ~state;
endcase
end
end
// Output logic
assign walk_left = (state == LEFT);
assign walk_right = (state == RIGHT);
endmodule
Lemmings2
查看代码
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah );
parameter LEFT = 3'b010, RIGHT = 3'b100, GND = 3'b001;
reg [2:0] state, next_state;
reg dir;
always @(*) begin
state = next_state;
end
always @(posedge clk or posedge areset) begin
if(areset) begin
next_state <= LEFT;
dir <= 0; //left
end
else begin
case(state)
LEFT: casex({bump_right, bump_left, ground})
3'bxx0: begin next_state <= GND; dir <= 0; end
3'bx11: next_state <= RIGHT;
default: next_state <= LEFT;
endcase
RIGHT: casex({bump_right, bump_left, ground})
3'bxx0: begin next_state <= GND; dir <= 1; end
3'b1x1: next_state <= LEFT;
default: next_state <= RIGHT;
endcase
GND: casex({bump_right, bump_left, ground})
3'bxx0: begin next_state <= GND; end
3'bxx1: next_state <= dir ? RIGHT : LEFT;
endcase
endcase
end
end
assign {walk_right, walk_left, aaah} = state;
endmodule
Fsm onehot
查看代码
module top_module(
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2);
//方法一：错误方法，next_state未被赋值的bit会维持之前的值
always @(in or state) begin
next_state = 0;
case(1'b1) // synthesis parallel_case
state[0]: if(in) next_state[1] = 1; else next_state[0] = 1;
state[1]: if(in) next_state[2] = 1; else next_state[0] = 1;
state[2]: if(in) next_state[3] = 1; else next_state[0] = 1;
state[3]: if(in) next_state[4] = 1; else next_state[0] = 1;
state[4]: if(in) next_state[5] = 1; else next_state[0] = 1;
state[5]: if(in) next_state[6] = 1; else next_state[8] = 1;
state[6]: if(in) next_state[7] = 1; else next_state[9] = 1;
state[7]: if(in) next_state[7] = 1; else next_state[0] = 1;
state[8]: if(in) next_state[1] = 1; else next_state[0] = 1;
state[9]: if(in) next_state[1] = 1; else next_state[0] = 1;
default: next_state = 0;
endcase
end
/*
//方法二：正确方法
assign next_state[0] = (!in)&(state[0] | state[1] | state[2] | state[3] | state[3] | state[4] | state[7] | state[8] | state[9]);
assign next_state[1] = in&(state[0] | state[8] | state[9]);
assign next_state[2] = in&(state[1]);
assign next_state[3] = in&(state[2]);
assign next_state[4] = in&(state[3]);
assign next_state[5] = in&(state[4]);
assign next_state[6] = in&(state[5]);
assign next_state[7] = in&(state[6] | state[7]);
assign next_state[8] = (!in)&(state[5]);
assign next_state[9] = (!in)&(state[6]);
*/
assign out2 = state[7] | state[9];
assign out1 = state[8] | state[9];
endmodule
Fsm ps2
查看代码
module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done); //
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b100;
reg [2:0] status, next_status;
// State transition logic (combinational)
always @(*) begin
status = next_status;
end
// State flip-flops (sequential)
always @(posedge clk) begin
if (reset) begin
next_status <= S0;
end
else begin
case (status)
S0: next_status <= in[3] ? S1 : S0;
S1: next_status <= S2;
S2: next_status <= S3;
S3: next_status <= in[3] ? S1 : S0;
endcase
end
end
// Output logic
assign done = status == S3;
endmodule
Fsm ps2data
查看代码
module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done); //
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b100;
reg [2:0] status, next_status;
// State transition logic (combinational)
always @(next_status) begin
status = next_status;
end
// State flip-flops (sequential)
always @(posedge clk) begin
if (reset) begin
next_status <= S0;
end
else begin
case (status)
S0: next_status <= in[3] ? S1 : S0;
S1: next_status <= S2;
S2: next_status <= S3;
S3: next_status <= in[3] ? S1 : S0;
endcase
end
end
// Output logic
assign done = status == S3;
// New: Datapath to store incoming bytes.
always @(posedge clk) begin
out_bytes[7:0] <= status == S2 ? in[7:0] : out_bytes[7:0];
out_bytes[15:8] <= status == S1 ? in[7:0] : out_bytes[15:8];
out_bytes[23:16] <= status == S3 ? in[7:0] : (status == S0 ? in[7:0] : out_bytes[23:16]);
end
endmodule
Verification: Reading Simulations
Finding bugs in code
159：Bugs mux2
查看代码
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output [7:0] out );
assign out = sel ? a: b;
endmodule
160：Bugs nand3
查看代码
module top_module (input a, input b, input c, output out);//
wire out0;
andgate inst1 ( out0, a, b, c, 1'b1, 1'b1 );
assign out = ~out0;
endmodule
161：Bugs mux4
查看代码
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out ); //
wire [7:0] mux0, mux1;
mux2 ins_mux0 ( sel[0], a, b, mux0 );
mux2 ins_mux1 ( sel[0], c, d, mux1 );
mux2 ins_mux2 ( sel[1], mux0, mux1, out );
endmodule
162：Bugs addsubz
查看代码
// synthesis verilog_input_version verilog_2001
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
);//
always @(*) begin
case (do_sub)
0: out = a+b;
1: out = a-b;
endcase
if (out==8'b0000_0000)
result_is_zero = 1;
else
result_is_zero = 0;
end
endmodule
163：Bugs case
查看代码
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid=1 );//
always @(*)
case (code)
8'h45: begin out = 0; valid = 1; end
8'h16: begin out = 1; valid = 1; end
8'h1e: begin out = 2; valid = 1; end
8'h26: begin out = 3; valid = 1; end
8'h25: begin out = 4; valid = 1; end
8'h2e: begin out = 5; valid = 1; end
8'h36: begin out = 6; valid = 1; end
8'h3d: begin out = 7; valid = 1; end
8'h3e: begin out = 8; valid = 1; end
8'h46: begin out = 9; valid = 1; end
default: begin out = 0; valid = 0; end
endcase
endmodule
Build circuits from a simulation waveofrm
164：Sim/circuit1
查看代码
module top_module (
input a,
input b,
output q );//
assign q = a & b; // Fix me
endmodule
165：Sim/circuit2
查看代码
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = ~(a ^ b ^ c ^ d); // Fix me
endmodule
166：Sim/circuit3
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module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = (a|b)&(c|d); // Fix me
endmodule
167：Sim/circuit4
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module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = b|c; // Fix me
endmodule
168：Sim/circuit5
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module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output [3:0] q );
always @(*) begin
case (c)
4'h0: q = b;
4'h1: q = e;
4'h2: q = a;
4'h3: q = d;
default: q = 4'hF;
endcase
end
endmodule
169：Sim/circuit6
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module top_module (
input [2:0] a,
output [15:0] q );
always @(*) begin
case (a)
3'h0: q = 16'h1232;
3'h1: q = 16'haee0;
3'h2: q = 16'h27d4;
3'h3: q = 16'h5a0e;
3'h4: q = 16'h2066;
3'h5: q = 16'h64ce;
3'h6: q = 16'hc526;
3'h7: q = 16'h2f19;
default: q = 16'h1232;
endcase
end
endmodule
170：Sim/circuit7
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module top_module (
input clk,
input a,
output q );
always @(posedge clk) begin
q <= ~a;
end
endmodule
171：Sim/circuit8
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module top_module (
input clock,
input a,
output p,
output q );
always @(negedge clock) begin
q <= a;
end
assign p = clock ? a : p;
endmodule
172：Sim/circuit9
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module top_module (
input clk,
input a,
output [3:0] q );
always @(posedge clk) begin
if(a==1'b1) q <= 4'h4;
else begin
if(q==4'h6) q <= 4'h0;
else q <= q + 4'h1;
end
end
endmodule
173：Sim/circuit10
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module top_module (
input clk,
input a,
input b,
output q,
output state );
always @(posedge clk) begin
if(~state) state = (a&b);
else state = (a|b);
end
assign q = state ? ~(a^b) : (a^b) ;
endmodule
Verification: Writing Testbenches
174：Tb/clock
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module top_module ( );
reg clk;
initial clk = 0;
always #5 clk = ~clk;
dut dut0 (clk);
endmodule
175：Tb/tb1
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module top_module ( output reg A, output reg B );//
initial begin
A = 0;
B = 0;
#10 A = 1;
#5 B = 1;
#5 A = 0;
#20 B = 0;
end
endmodule
176：Tb/and
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module top_module();
reg [1:0] in;
wire out;
initial fork
#0 in = 2'b00;
#10 in = 2'b01;
#20 in = 2'b10;
#30 in = 2'b11;
join
andgate ins0(in, out);
endmodule
177：Tb/tb2
查看代码
module top_module();
reg clk;
reg in;
reg [2:0] s;
wire out;
initial fork
clk = 0;
in = 0;
#20 in = 1;
#30 in = 0;
#40 in = 1;
#70 in = 0;
s = 3'b010;
#10 s = 3'b110;
#20 s = 3'b010;
#30 s = 3'b111;
#40 s = 3'b000;
join
always #5 clk = ~clk;
q7 ins0(clk, in, s, out);
endmodule
参考
https://gitee.com/maicheal/hdlbits_-practice/tree/Modules_Hierarchy
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