sim_simple 

 1 `timescale 1ns / 1ps
 2 //////////////////////////////////////////////////////////////////////////////////
 3 //sim_sample.v
 4 //////////////////////////////////////////////////////////////////////////////////
 5 
 6 
 7 module sim_sample(
 8     input clk,
 9     input reset,
10     input [7:0] dat_in,
11     input enable,
12     output reg [9:0] comp_cnt
13     );
14     reg [7:0]   dat_in_dl;
15     always @ (posedge clk or posedge reset )
16         begin
17             if (reset)
18                 begin
19                     dat_in_dl   <= 8'h00;
20                     comp_cnt    <= 10'd0;                    
21                 end
22             else if (enable)
23                 begin
24                     dat_in_dl   <= dat_in;
25                     if (dat_in_dl == dat_in )
26                         comp_cnt    <=  comp_cnt + 1;
27                 end    
28         end 
29 endmodule

 

 1 `timescale 1ns / 1ps
 2 //////////////////////////////////////////////////////////////////////////////////
 3 //  tb_sim_sample
 4 //////////////////////////////////////////////////////////////////////////////////
 5 
 6 
 7 module tb_sim_sample_2;
 8 parameter       QUANT_VECTORS   = 32; // quantity of vector samples
 9 // input signal to the test module
10 reg         reset;
11 reg         sim_clk;
12 reg [7:0]   dat_in;
13 reg         enable;
14 reg [31:0]  random_num;
15     // output signals from the test module
16 wire [9:0]  comp_cnt;
17 
18 // testbench signals
19 integer     i;
20 integer     j;
21 
22 // clock periods
23 parameter   CLK_PERIOD = 10; // 10 ns = 100 MHz
24 
25 // ------------ Design implementation
26 
27 // module under test
28 sim_sample      mut
29     (
30     .clk        ( sim_clk   ),
31     .reset      ( reset     ),
32     .dat_in     ( dat_in    ),
33     .enable     ( enable    ),
34     .comp_cnt   ( comp_cnt  )
35     ); 
36 
37 // generate clock and reset
38 
39 initial sim_clk = 1'b0;
40 
41 always #(   CLK_PERIOD/2.0  )
42     sim_clk = ~sim_clk;
43     
44 initial reset = 1'b1;
45 initial i = 0;
46 
47 // reset goes inactive after  20 clocks
48 always @ (posedge sim_clk)
49     begin
50         i = i + 1;
51         if (i == 20)
52             #1 reset <= 1'b0;
53     end        
54 
55 // feed stimulus vectors to module under test
56 initial begin
57     dat_in      = 8'b0;
58     enable      = 1'b0;
59     random_num  = $random(1);    
60         //
61     wait (reset);
62     wait (~reset);
63     @(posedge sim_clk)
64     for ( j = 0; j< 20 ; j = j+ 1)
65         begin
66             @ (posedge sim_clk);
67         end
68     
69     enable = 1'b1;
70     dat_in  = 8'h00;
71     //
72     for (j = 0; j< ( QUANT_VECTORS) ; j = j+ 1)
73         begin
74             @ (posedge sim_clk);
75             random_num = $random;
76             if (random_num[2:0] != 3'h0)
77                 dat_in = dat_in + 1;
78         end
79  
80     //
81     @ (posedge sim_clk);
82     enable  = 1'b0;
83     
84     forever 
85         begin
86             @ (posedge sim_clk)
87             enable = 1'b0; 
88         end            
89 end
90 
91 endmodule

 

 

 

 

 

posted @ 2017-03-22 09:19  souwang  阅读(236)  评论(0)    收藏  举报