SV_18_System Task and Function

引言：在verilog中已有的系统函数：

1. $display
2. $monitor
3. $finish
4. $readmemh 以及 $readmemb ：都是从文件中读取数据，二进制和十六进制的区别
5. $random
6. ...

SV增添的：

1. array system tasks
2. variables system tasks
3. assertion system tasks
4. random number system tasks
5. coverage system tasks
6. improved verilog system tasks
7. packed array system tasks
8. ...

1 Array system tasks

该类系统任务的返回类型是integer，可选维度表达式的默认值是1；

• $dimensions：
  • 对于packed、unpacked、static、dynamic类型，返回数组中维度的总数；
  • 对于字符串类型或任何 其他非array类型，相当于一个简单位向量，返回1；
  • 对于其他类型，返回0；
• $unpacked_dimensions：
  • 对于unpacked array（statc 或 dynamic），返回总的维数；
  • 对于其他类型，返回0；
• $left：返回维度的左边界；
• $right：返回维度的右边界；
• $low：返回$left和$right的最小值；
• $high：返回 $left和$right的最大值；
• $increment：
  • 如果$left大于等于$right，返回1；否则返回0；
• $size：返回元素总数，相当于$high - $low + 1

module system_array();
// 1 dimension
reg [7:0] me = 10;
// 2 dimension array of Verilog 2001
reg [7:0] mem [0:3] = '{8'h0,8'h1,8'h2,8'h3};
// one more example of multi dimention array
reg [7:0] mem1 [0:1] [0:3] = 
   '{'{8'h0,8'h1,8'h2,8'h3},'{8'h4,8'h5,8'h6,8'h7}};
// One more example of multi dimention array
reg [7:0] [0:4] mem2 [0:1] = 
   '{{8'h0,8'h1,8'h2,8'h3},{8'h4,8'h5,8'h6,8'h7}};
// One more example of multi dimention array
reg [7:0] [0:4] mem3 [0:1] [0:1]  = 
   '{'{{8'h0,8'h1,8'h2,8'h3},{8'h4,8'h5,8'h6,8'h7}},
   '{{8'h0,8'h1,8'h2,8'h3},{8'h4,8'h5,8'h6,8'h7}}};
// Multi arrays in same line declaration
bit [7:0] [31:0] mem4 [1:5] [1:10], mem5 [0:255]; 

initial begin
  // $dimensions usage
  $display ("$dimensions in me %0d mem %0d mem1 %0d",
     $dimensions(me),$dimensions(mem),$dimensions(mem1));
  // $unpacked_dimensions
  $display ("$unpacked_dimensions in me %0d mem %0d mem1 %0d",
     $unpacked_dimensions(me),$unpacked_dimensions(mem),
     $unpacked_dimensions(mem1));
  // $left
  $display ("$left in me %0d mem %0d mem1 %0d",
     $left(me),$left(mem),$left(mem1));
  // $right
  $display ("$right in me %0d mem %0d mem1 %0d",
     $right(me),$right(mem),$right(mem1));
  // $low
  $display ("$low in me %0d mem %0d mem1 %0d",
     $low(me),$low(mem),$low(mem1));
  // $high
  $display ("$high in me %0d mem %0d mem1 %0d",
     $high(me),$high(mem),$high(mem1));
  // $increment
  $display ("$increment in me %0d mem %0d mem1 %0d",
     $increment(me),$increment(mem),$increment(mem1));
  // $size
  $display ("$size in me %0d mem %0d mem1 %0d",
     $size(me),$size(mem),$size(mem1));

  #1 $finish;
end

endmodule

//simulation
 $dimensions in me 1 mem 2 mem1 3
 $unpacked_dimensions in me 0 mem 0 mem1 0
 $left in me 7 mem 0 mem1 0
 $right in me 0 mem 3 mem1 1
 $low in me 0 mem 0 mem1 0
 $high in me 7 mem 3 mem1 1
 $increment in me 1 mem -1 mem1 -1
 $size in me 8 mem 4 mem1 2

 

2 Variable system tasks

• $typename：返回一个表示参数类型的字符串；
• $size,$bits：返回变量的bit大小；
• $isunbounded：如果参数是$(无边界)，则返回true；

module system_variable();

  bit signed [2:0] abc;
  int signed       xyz;
  enum {A,B,C=99}  enm;

  typedef struct {bit [7:0] A,B;} AB_t;
  AB_t AB[10]; 

  parameter int foo = $;

initial begin
  // $typename usage
  $display ("$typename of abc  %s",$typename(abc));
  $display ("$typename of xyz  %s",$typename(xyz));
  $display ("$typename of enm  %s",$typename(enm));
  $display ("$typename of AB_t %s",$typename(AB_t));
  $display ("$typename of AB   %s",$typename(AB));
  $display ("$typename of foo  %s",$typename(foo));
  // $bits usage
  $display ("$bits     of abc  %0d",$bits(abc));
  $display ("$bits     of xyz  %0d",$bits(xyz));
  $display ("$bits     of enm  %0d",$bits(enm));
  $display ("$bits     of AB_t %0d",$bits(AB_t));
  $display ("$bits     of AB   %0d",$bits(AB));
  $display ("$bits     of foo  %0d",$bits(foo));
  // $isunbounded
  $display ("$isunbounded of abc  %0d",$isunbounded(abc));
  $display ("$isunbounded of xyz  %0d",$isunbounded(xyz));
  $display ("$isunbounded of enm  %0d",$isunbounded(enm));
  $display ("$isunbounded of AB   %0d",$isunbounded(AB));
  $display ("$isunbounded of foo  %0d",$isunbounded(foo));
end

endmodule

//simulation
    
 $typename of abc  bit signed[2:0]
 $typename of xyz  int
 $typename of enm  enum system_variable.unnamed$$
 $typename of AB_t struct system_variable.AB_t
 $typename of AB   struct system_variable.AB_t$[0:9]
 $typename of foo  int
 $bits     of abc  3
 $bits     of xyz  32
 $bits     of enm  32
 $bits     of AB_t 16
 $bits     of AB   160
 $bits     of foo  32
 $isunbounded of abc  0
 $isunbounded of xyz  0
 $isunbounded of enm  0
 $isunbounded of AB   0
 $isunbounded of foo  1

 

3 Assertion system tasks

• $assertoff：停止检查所有指定的断言，直到出现后续的$asserton。已在执行的断言不受影响；
• $assertkill：中止当前正在执行断言的执行，然后停止检查所有断言，直到后续出现$asserton；
• $asserton：重启所有指定的断言；
• $fatal；打印运行时致命错误，会自动隐式调用$finish；
• $error：打印运行错误；
• $warning：运行时的警告，可以用工具对其抑制；
• $info：打印没有严重性的断言信息。

module system_assert();

reg  clk, grant, request;
time current_time;

initial begin
  clk = 0;
  grant   = 0;
  request = 0;
  #4 request = 1;
  #4 grant = 1;
  #4 request = 0;
  #4 grant = 0;
  #4 request = 0;
  #4 grant = 1;
  #4 request = 0;
  #4 $finish;
end

always #1 clk = ~clk;
//=================================================
// Assertion used in always block
//=================================================
always @ (posedge clk)
begin
  if (grant == 1) begin
     CHECK_REQ_WHEN_GNT : assert (grant && request) begin
        $info("Seems to be working as expected");
     end else begin
        current_time = $time;
        // We can use all below statements
        //    $fatal
        //    $error
        //    $warning
        //    $info
        #1 $warning("assert failed at time %0t", current_time);
        $assertoff(1,system_assert.CHECK_REQ_WHEN_GNT);
     end
  end
end

endmodule

//simulation
 Info: "system_assert.sv", 27: system_assert.CHECK_REQ_WHEN_GNT: at time 9
 Seems to be working as expected
 Info: "system_assert.sv", 27: system_assert.CHECK_REQ_WHEN_GNT: at time 11
 Seems to be working as expected
 "system_assert.sv", 27: system_assert.CHECK_REQ_WHEN_GNT: started at 13s failed at 13s
         Offending '(grant && request)'
 Warning: "system_assert.sv", 27: system_assert.CHECK_REQ_WHEN_GNT: at time 14
 assert failed at time 13
 Stopping new attempts for assertion CHECK_REQ_WHEN_GNT at time 14s.

 

4 Random number system tasks

• $urandom_range：产生一组在特定范围的无符号integer数；
• $urandom：每次调用都会返回一个新的无符号的32位随机数；
• $random：为随机对象引入RNG（random number generator）；
• $set_randstate：设置RNG的状态；
• $get_randstate：获取当前的RNG状态。

module system_random();

initial begin
 // Set the seed
 $srandom(10);
 // Randomize number between 1 and 10
 $display ("Value is %0d",$urandom_range(10,1));
 // Use seed 10 before randomize
 $display ("Value is %0d",$urandom(10));
end

endmodule

//simulation
 Value is 7
 Value is 1259199836

 

5 Coverage system tasks

• $coverage_contral：用于控制或查询层次结构中指定部分的覆盖率可用性；
• $coverage_get_max：获得在层次结构的指定部分上指定覆盖率类型的100%覆盖率的值；
• $coverage_get：获得在层次结构指定部分的给定覆盖类型的当前覆盖值；
• $coverage_merge：将指定覆盖率合并到模拟器中；
• $coverage_save：将当前覆盖率的状态保存到工具的覆盖率数据库中，并将其与给定的名称相关联；

module system_coverage();

reg  clk, reset,enable;

reg [3:0] cnt;

always @ (posedge clk)
  if (reset) 
    cnt <= 0;
  else if (enable)
    cnt <= cnt + 1;

initial begin
  // Disable coverage before reset
  $coverage_control(`SV_COV_STOP,`SV_COV_STATEMENT,`SV_COV_HIER,$root);
  clk    <= 0;
  reset  <= 1;
  enable <= 0;
  $monitor("Count %0d",cnt);
  repeat (4) @ (posedge clk);
  reset  <= 0;
  // Enable coverage after reset
  $coverage_control(`SV_COV_START,`SV_COV_STATEMENT,`SV_COV_HIER,$root);
  enable <= 1;
  repeat (4) @ (posedge clk);
  enable <= 0;
  #4 $finish;
end

always #1 clk = ~clk;

endmodule