如何在缺少FPGA硬件的情况下学习数字电路
数字电路课程的学习早已经不可能忽视Verilog HDL的设计了,如果以后考研读通信、信号处理等方向的专业硕士(专硕)的话,就更是必备的技能。但是在手头暂时没有FPGA硬件的情况下,Verilog HDL不能落地,此时如何想办法弥补呢?单纯的Protesu仿真是不够的,因为Proteus库中缺少FPGA,只能退而求其次,Proteus中选择古老的MSI进行仿真,同时Diamond中进行Verilog设计,ModelSim中做功能仿真。下面以显示译码器为例,讲解学习过程。
1. Diamond编写Verilog code和testbench
module seg7 (bcd, leds); input [3:0] bcd; output reg [1:7] leds; always @(bcd) case (bcd) //abcdefg 0: leds = 7'b1111110; 1: leds = 7'b0110000; 2: leds = 7'b1101101; 3: leds = 7'b1111001; 4: leds = 7'b0110011; 5: leds = 7'b1011011; 6: leds = 7'b1011111; 7: leds = 7'b1110000; 8: leds = 7'b1111111; 9: leds = 7'b1111011; default: leds = 7'bx; endcase endmodule
`timescale 1ns/100ps module seg7_tb (); reg [3:0] bcd; wire [1:7] leds; //abcdefg initial begin bcd = 0; #20 bcd = 1; #20 bcd = 2; #20 bcd = 3; #20 bcd = 4; #20 bcd = 5; #20 bcd = 6; #20 bcd = 7; #20 bcd = 8; #20 bcd = 9; #40; end seg7 dut ( .bcd(bcd), .leds(leds) ); endmodule
2. Modelsim中仿真,适合驱动共阴极数码管(正逻辑)
3. Arduino编写生成测试信号的程序,即依次产生0~9(8421BCD)
void setup() { pinMode(13, OUTPUT); //MSB pinMode(12, OUTPUT); pinMode(11, OUTPUT); pinMode(10, OUTPUT); //LSB } void loop() { digitalWrite(13, LOW); digitalWrite(12, LOW); digitalWrite(11, LOW); digitalWrite(10, LOW); delay(500); digitalWrite(13, LOW); digitalWrite(12, LOW); digitalWrite(11, LOW); digitalWrite(10, HIGH); delay(500); digitalWrite(13, LOW); digitalWrite(12, LOW); digitalWrite(11, HIGH); digitalWrite(10, LOW); delay(500); digitalWrite(13, LOW); digitalWrite(12, LOW); digitalWrite(11, HIGH); digitalWrite(10, HIGH); delay(500); digitalWrite(13, LOW); digitalWrite(12, HIGH); digitalWrite(11, LOW); digitalWrite(10, LOW); delay(500); digitalWrite(13, LOW); digitalWrite(12, HIGH); digitalWrite(11, LOW); digitalWrite(10, HIGH); delay(500); digitalWrite(13, LOW); digitalWrite(12, HIGH); digitalWrite(11, HIGH); digitalWrite(10, LOW); delay(500); digitalWrite(13, LOW); digitalWrite(12, HIGH); digitalWrite(11, HIGH); digitalWrite(10, HIGH); delay(500); digitalWrite(13, HIGH); digitalWrite(12, LOW); digitalWrite(11, LOW); digitalWrite(10, LOW); delay(500); digitalWrite(13, HIGH); digitalWrite(12, LOW); digitalWrite(11, LOW); digitalWrite(10, HIGH); delay(500); }
4. Proteus中选择74'47驱动共阳极数码管(负逻辑),用逻辑分析仪生成波形
5. 比对ModelSim和Proteus的波形,若一致(此处二者输出逻辑是相反的,这样更有助于思考),证明Verilog设计无误,与最终在FPGA上实现仅相差配置引脚和下载。
Extra 6. 如果以后有了FPGA,进一步的做法是,配置引脚(前提是熟悉FPGA电路图),生成JEDEC文件并下载到FPGA中,与Arduino联调。
此处以step-MAXO2开发板为例,板载两个数码管,对应引脚如下两图所示;BCD输入需选择空闲引脚,此处选择13、12、11、10。另外需要指出的是,下图中并未将共阴极引脚(SEG_DIG1,C9)包含其中,在实际开发中,务必配置该引脚。
Extra 7. 下载程序