stm32f107使用内部晶振

注释掉

//#define SYSCLK_FREQ_72MHz  72000000

同时修改：

void SystemInit (void)
{
#if 0
RCC_DeInit();
RCC_HSICmd(ENABLE); //¿ªÆôÄÚ²¿¸ßËÙÕñµ´Æ÷
while(RCC_GetFlagStatus(RCC_FLAG_HSIRDY)== RESET){//µÈ´ýHSI¾Í¾w
}

RCC_HCLKConfig(RCC_SYSCLK_Div1); //ÉèÖÃAHBʱÖÓ(HCLK) RCC_SYSCLK_Div1 AHBʱÖÓµÈÓÚϵͳʱÖÓ
RCC_PCLK2Config(RCC_HCLK_Div1); //ÉèÖøßËÙAPBʱÖÓ(PCLK2) RCC_HCLK_Div1 APB2µÈÓÚHCLK
RCC_PCLK1Config(RCC_HCLK_Div2); //ÉèÖõÍËÙAPBʱÖÓ(PCLK1) RCC_HCLK_Div2 APB1µÈÓÚHCLK/2

/* Enable refetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;

/* Flash 2 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;

//FLASH_SetLatency(FLASH_Latency_2); //ÉèÖÃFLASHÑÓʱÁ½¸öÖÜÆÚ
// FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); //ʹÄÜԤȡָÁ³åÆ÷

RCC_PLLConfig(RCC_PLLSource_HSI_Div2,RCC_PLLMul_9);//ÄÚ²¿8M¶þ·ÖƵ×÷ΪPLLʱÖÓÔ´£¬PLL±¶Æµ16 LLCLK=64MHZ
RCC_PLLCmd(ENABLE); //ʹÄÜPLLʱÖÓ
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) ;

RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); //Ñ¡ÔñPLLCLKΪϵͳʱÖÓ
while(RCC_GetSYSCLKSource() != 0x08); //µÈ´ýPLLCLKÉèÖÃΪϵͳʱÖÓ
#endif
#if 0
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;

/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#ifndef STM32F10X_CL
RCC->CFGR &= (uint32_t)0xF8FF0000;
#else
RCC->CFGR &= (uint32_t)0xF0FF0000;
#endif /* STM32F10X_CL */

/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;

/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;

/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;

#ifdef STM32F10X_CL
/* Reset PLL2ON and PLL3ON bits */
RCC->CR &= (uint32_t)0xEBFFFFFF;

/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x00FF0000;

/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;

/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#else
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
#endif /* STM32F10X_CL */

#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
#endif

/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
/* Configure the Flash Latency cycles and enable prefetch buffer */
SetSysClock();

#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif
#endif

/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;

// select HSI as PLL source
RCC->CFGR |= (uint32_t)RCC_CFGR_PLLSRC_HSI_Div2;

//PLLCLK=8/2*9=36M
RCC->CFGR |= (uint32_t)RCC_CFGR_PLLMULL9;

/* HCLK = SYSCLK/1 */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;

/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
}