Vivado_8位流水灯

Design

代码中的计数器设置是因为我的开发板的时钟是100MHZ的,也就是1秒完成了100_000_000次时钟信号,所以我设置计数器为100_000_000次。

也就是说,我让流水灯的变化周期为1 s。

counter == 32'd100_000_000

代码

`timescale 1ns / 1ps
module flow_led(
    clk, 
    reset, 
    led 
);
input clk;
input reset;
output [7:0] led;

reg [7:0] led;
reg [31:0] counter; 
reg [1:0] state; 


always @(posedge clk or negedge reset)
    begin
        if(!reset) 
            begin
                counter <= 32'd0;
            end
        else if ( counter == 32'd100_000_000) //change T
            begin
                counter <= 32'd0;
            end
        else 
            begin
                counter <= counter + 32'd1;
            end
        end
        

always @(posedge clk or negedge reset)
    begin
        if(!reset) 
            begin
                state <= 1'd0;
            end
        else if( counter == 32'd0 )
            begin
            state <= 1'd1;
            end
        else
            begin
            state <= 1'd0;
            end
        
    end
    

always @(posedge clk or negedge reset)
    begin
        if(!reset) 
            begin
                led <= 8'b1111_1111;
            end
        else 
            begin
                if(state == 1'd1)
                begin
                    if(led == 8'b1111_1111)
                    begin
                        led <= 8'b0000_0001;
                    end
                    else if(led == 8'b1000_0000)
                    begin
                        led <= 8'b0000_0001;
                    end
                    else
                    begin
                        led <= led << 1'b1;
                    end
                end
            end
    end

endmodule

Simulation

若在波形仿真中,我们想让与模拟的时钟信号也是100MHZ,让流水灯的周期也为1s,那样的话仿真是跑不完的。

所以我们先修改刚刚的计数周期:

counter == 32'd1_000_000

仿真中让时钟周期为1000 ns

parameter T=1000;

这样就可以很轻松的看到流水灯全周期的波形图了。

代码

`timescale 1ns/1ns
module sim_dev1();
parameter T=1000;
reg clk;
reg reset;
wire [7:0] led;

initial 
begin
clk=1'b0;
reset=1'b0;
#(T+1) reset=1'b1;
end

always #(T/2) clk=~clk;
flow_led u1(
.clk(clk),
.reset(reset),
.led(led)
);

endmodule

波形图

参考资料

posted @ 2022-11-04 10:59  江水为竭  阅读(390)  评论(0编辑  收藏  举报