systemverilog中iff的用法总结

在uvm里面的使用：
功能覆盖率的时候使用:

covergroup cg_apb_command @(posedge clk iff rstn);
endgroup

monitor的时候使用：

task apb_master_monitor::collect_transfer();
  // Advance clock
  @(vif.cb_mon iff (vif.cb_mon.psel === 1'b1 && vif.cb_mon.penable === 1'b0));
endtask

RTL设计代码：
9.2.2.4 Sequential logic always_ff procedure
The always_ff procedure can be used to model synthesizable sequential logic behavior. For example:

always_ff @(posedge clock iff reset == 0 or posedge reset) begin
  r1 <= reset ? 0 : r2 + 1;
  ...
end

9.4 Procedural timing controls
event_expression ::=
[ edge_identifier ] expression [ iff expression ]
| sequence_instance [ iff expression ]
| event_expression or event_expression
| event_expression , event_expression
| ( event_expression )

9.4.2.3 Conditional event controls
The @ event control can have an iff qualifier.

module latch (output logic [31:0] y, input [31:0] a, input enable);
  always @(a iff enable == 1)
    y <= a; //latch is in transparent mode
endmodule