systemverilog中层次与路径的区别

uvm_top = uvm_root::type_id::create("__top__", null);
uvm_test_top = my_casen::type_id::create("uvm_test_top", this);
env = my_env::type_id::create("env", this);
i_agt = my_agent::type_id::create("agt", this);
层次结构：uvm_test_top.env.i_agt;
路径：uvm_test_top.env.agt;
i_agt = my_agent::type_id::create("agt", this);
get_name();------->agt;
get_full_name();-->uvm_test_top.env.agt;
get_type();------->i_agt;
get_type_name();-->my_agt;