UVM寄存器读写检查中跳过某个寄存器

UVM提供两个sequence分别用于检查寄存器和存储器的读写功能；
1.uvm_reg_hw_reset_seq用于检查上电复位后寄存器模型与DUT中寄存器的默认值是否相同；
2.uvm_reg_access_seq用于检查寄存器的读写；
3.uvm_mem_access_seq用于检查存储器的读写。
如果要跳过某个寄存器或存储器的检查，可以使用以下方法：

function void my_case0::build_phase(uvm_phase phase);
   super.build_phase(phase);
   uvm_resource_db#(bit)::set({"REG::",rm.invert.get_full_name(),".*"},
                              "NO_REG_TESTS", 1, this);
   uvm_resource_db#(bit)::set({"REG::",regmodel.blk.mem0.get_full_name()},
                              "NO_MEM_TESTS", 1, this);
endfunction

每一种reg或mem可以使用的跳过寄存器的方法：

// class: uvm_mem_single_access_seq
// If bit-type resource named
// "NO_REG_TESTS" or "NO_REG_BIT_BASH_TEST"
// in the "REG::" namespace
// matches the full name of the register,
// the register is not tested.
// "NO_REG_TESTS", "NO_MEM_TESTS", or "NO_MEM_ACCESS_TEST"
//| uvm_resource_db#(bit)::set({"REG::",regmodel.blk.mem0.get_full_name()},
//|                            "NO_MEM_TESTS", 1, this);

// Class: uvm_reg_bit_bash_seq
// If bit-type resource named
// "NO_REG_TESTS" or "NO_REG_BIT_BASH_TEST"
// in the "REG::" namespace
// matches the full name of the block,
// the block is not tested.
//| uvm_resource_db#(bit)::set({"REG::",regmodel.blk.get_full_name(),".*"},
//|                            "NO_REG_TESTS", 1, this);

// class: uvm_mem_access_seq
// "NO_REG_TESTS", "NO_MEM_TESTS", or "NO_MEM_ACCESS_TEST"
//| uvm_resource_db#(bit)::set({"REG::",regmodel.blk.get_full_name(),".*"},
//|                            "NO_MEM_TESTS", 1, this);

// Class: uvm_mem_single_walk_seq
// "NO_REG_TESTS", "NO_MEM_TESTS", or "NO_MEM_WALK_TEST"
//| uvm_resource_db#(bit)::set({"REG::",regmodel.blk.mem0.get_full_name()},
//|                            "NO_MEM_TESTS", 1, this);

// Class: uvm_mem_walk_seq
// "NO_REG_TESTS", "NO_MEM_TESTS", or "NO_MEM_WALK_TEST"
//| uvm_resource_db#(bit)::set({"REG::",regmodel.blk.get_full_name(),".*"},
//|                            "NO_MEM_TESTS", 1, this);

// Class: uvm_reg_single_access_seq
// "NO_REG_TESTS" or "NO_REG_ACCESS_TEST"
//| uvm_resource_db#(bit)::set({"REG::",regmodel.blk.r0.get_full_name()},
//|                            "NO_REG_TESTS", 1, this);

// Class: uvm_reg_access_seq
// "NO_REG_TESTS" or "NO_REG_ACCESS_TEST"
//| uvm_resource_db#(bit)::set({"REG::",regmodel.blk.get_full_name(),".*"},
//|                            "NO_REG_TESTS", 1, this);

// Class: uvm_reg_single_bit_bash_seq
// "NO_REG_TESTS" or "NO_REG_BIT_BASH_TEST"
//| uvm_resource_db#(bit)::set({"REG::",regmodel.blk.r0.get_full_name()},
//|                            "NO_REG_TESTS", 1, this);

// Class: uvm_reg_bit_bash_seq
// "NO_REG_TESTS" or "NO_REG_BIT_BASH_TEST"
//| uvm_resource_db#(bit)::set({"REG::",regmodel.blk.get_full_name(),".*"},
//|                            "NO_REG_TESTS", 1, this);

// class: uvm_reg_hw_reset_seq
// "NO_REG_TESTS" or "NO_REG_HW_RESET_TEST"
//| uvm_resource_db#(bit)::set({"REG::",regmodel.blk.get_full_name(),".*"},
//|                            "NO_REG_TESTS", 1, this);

// Class: uvm_reg_shared_access_seq
// "NO_REG_TESTS" or "NO_REG_SHARED_ACCESS_TEST"
//| uvm_resource_db#(bit)::set({"REG::",regmodel.blk.r0.get_full_name()},
//|                            "NO_REG_TESTS", 1, this);

// Class: uvm_mem_shared_access_seq
// "NO_REG_TESTS", "NO_MEM_TESTS",
// "NO_REG_SHARED_ACCESS_TEST" or "NO_MEM_SHARED_ACCESS_TEST"
//| uvm_resource_db#(bit)::set({"REG::",regmodel.blk.mem0.get_full_name()},
//|                            "NO_MEM_TESTS", 1, this);

// Class: uvm_reg_mem_shared_access_seq
// "NO_REG_TESTS", "NO_MEM_TESTS",
// "NO_REG_SHARED_ACCESS_TEST" or "NO_MEM_SHARED_ACCESS_TEST"
//| uvm_resource_db#(bit)::set({"REG::",regmodel.blk.get_full_name(),".*"},
//|                            "NO_REG_TESTS", 1, this);