VCS中编译和运行主要选项

compile:
vcs

1. -full64
   //Enables compilation and simulation in 64-bit mode.
2. -sverilog
   //Enables the analysis of SystemVerilog source code.
3. -ntb_opts uvm-1.1
   //This version of VCS provides native support for UVM-1.1d. These libraries are located in:
   •$VCS_HOME/etc/uvm-1.1
   UVM 1.1 is now replaced with UVM 1.1d, which is the default. You can load UVM 1.1d by:
   •Using the -ntb_opts uvm option
   •Explicitly specifying the -ntb_opts uvm-1.1 option
4. +incdir+directory
   //Specifies the directories that contain the files specified with the ‘include compiler directive. You can specify more than one directory, separating each path name with the “+” character.
5. +define+macro
   //Defines a text macro. Test this definition in your Verilog source code using the ‘ifdef compiler directive.
6. -lca
   //这是VCS的参数，表示使用VCS的“用户限制使用”的功能，即VCS提供的一些功能是他们还没有经过充分测试还没有发布的；如果你想使用这些功能就要加上 -lca参数。
7. -kdb
   //With the integration of Certitude, VCS, and Verdi, you can load designs automatically in the Verdi system without setting the Certitude VerdiInitCommand configuration option.
   如果要支持Verdi，需要设置好NOVAS_LIB_PATH的环境变量，并且在命令行中添加-kdb的option，knowledge database（kdb）是VCS支持Verdi时的重要概念。
8. -o [executable]
   By default, VCS MX generates the binary executable simv. However, you can use the compile time option, -o with the vcs command line to generate the binary executable with the specified name.
9. -l <compile.log>
   //指定编译时生成log的名字
10. -timescale=time_unit/time_precision
    This option enables you to specify the timescale for the source files that do not contain ‘timescale compiler directive and precede the source files that contain.
    Do not include spaces when specifying the arguments to this option.
11. -cm line|cond|fsm|tgl|branch|assert
    -cm line+cond+fsm+tgl+branch+assert
    Specifies compiling for the specified type or types of coverage.
12. -cm_dir <directory_path_name>
    Specifies an alternative name and location for the coverage database directory.
13. -cm_hier <file_name>
    when compiling for line, condition, FSM or toggle coverage, sepcifies a configuration file that specifies module definitions, source files or module instances and their subhierarchies, that you want VCS to exclude from coverage or be the only of the design compiled for coverage.
14. -y <directory_pathname>
    Specifies a Verilog library directory to search for module definitions.
15. -v
    Specifies a Verilog library file to search for module definitions.
16. +libext+
    Specifies that VCS only search the source file in a Verilog library directory with the specified extension. You can specify more than one extension, separating each extension with the + character.For example, +libext++.v specifies searches library files with no extention and library files with the .v extension. Enter this option when you enter the -y option.
17. -debug_access+all
    //Batch Mode
    You can compile your design in batch mode, also called as optimized mode, when most of your design issues are resolved. In this phase, you can achieve better performance to run regressions and with minimum debug abilities.
    Note:
    The runtime performance reduces if you use -debug, -debug_all, or -debug_access(+). Use these options only when you require runtime debug abilities.

VCS MX provides the following compile-time options for the debug mode:
-debug_pp, -debug, -debug_access(+), -debug_all, -debug_region=()(+)
The following examples show how to compile the design in full, partial, and minimum debug modes:

Elaborating the Design in the Partial Debug Mode
vcs -debug [compile_options] TOP
Elaborating the Design in the Full Debug Mode
vcs -debug_all [compile_options] TOP
Elaborating the Design With the Desired Debug Capability
vcs -debug_access<+options> [compile_options] TOP
You can use the -debug_access option at compile time to have more granular control over debug capabilities in a simulation.
The -debug_access option enables the dumping of the VPD and FSDB files for post-processing debug, and reduces debug capabilities when compared to the -debug_pp option.
You can specify additional options with the -debug_access option to selectively enable the required debug capabilities. You can optimize simulation performance by enabling only the required debug capabilities.
-debug_region+cell+encrypt # 允许dump cell的波形(stdcell, memory cell等)；
The -debug_access+all option is equivalent to the following commands:
-debug_access+line+class+wn+driver+r+w+cbk+f+fn+thread+cbkd
The -debug_access+all option enables debug capabilities equal to -debug_all (except it does not apply capability inside cells and encrypted modules).
run:
./simv

1. +UVM_TESTNAEM=<case_name>
   //指定testcase名字
2. +ntb_random_seed=
   //指定seed
3. +UVM_VERBOSITY=
   //指定信息冗余度的程度
4. -l <run_time.log>
   //指定运行时log的名字
5. -cm line|cond|fsm|tgl|branch|assert
   Specifies elaborating for the specified type or types of coverage. The argument specifies the types of coverage:
   line
   Elaborate for line or statement coverage.
   cond
   Elaborate for condition coverage.
   fsm
   Elaborate for FSM coverage.
   tgl
   Elaborate for toggle coverage.
   branch
   Elaborate for branch coverage
   assert
   Elaborate for SystemVerilog assertion coverage.
6. -cm_name <coverage_name>
   Specifies unique name of that test during simulation.
7. -cm_log <coverager_log_name>
   Specifies a log file for monitoring for coverage during simulation.
8. -cm_dir <directory_path_name>
   Specifies an alternative name and location for the coverage database directory.

VCS中dump波形：
initial begin
$fsdbDumpfile("sim.fsdb");
$fsdbDumpvars(0, top, "+all");
end