摘要:
1、Warning (12125): Using design file div.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project原因:模块不是在本项目生成的,而是直接copy了别的项目的原理图和源程序而生成的,而不是用QUARTUS将文件添加进本项目 措施:无须理会,不影响使用2、Warning (10230): Verilog HDL assignment warni 阅读全文