基本时序逻辑电路练习

　　基本时序逻辑电路

　　·  D触发器

　　·  JK触发器

　　·  移位寄存器

　　·  计数器

　　·  分频器

　　·

 

　　在基本时序逻辑电路的编写中，最常见的是这样几种警告：

　　(1): Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

　　(2): Critical Warning: No exact pin location assignment(s) for 4 pins of 4 total pins
　　(3): Critical Warning: Synopsys Design Constraints File file not found: 'JK_Flipflop.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

　　(4): Critical Warning: Timing requirements not met