摘要：`timescale 1ns/1ps module tb_top (); reg clk ; //10MHz reg i_adc_dout1 ; reg i_adc_dout2 ; wire o_cnvst_n ; wire o_sclk ; wire tx ; reg [13:0] adc_i [ 阅读全文

摘要：clear;close all;clc; % 读取数据txt（任意进制、整型、浮点型）fileID1 = fopen('D:\设计文档\dataset1_I.txt','r');[dat_i]=textscan(fileID1,'%f');fclose(fileID1); fileID2 = fop 阅读全文