以3种方式描述3人表决器件(其中也涉及到了模块化编程)

选自《《基于VHDL的FPGA和NoisII实例精炼》》

一

--*************第一种方式*******************
--数据流方式，主要用于简单的逻辑功能的实现，以信号赋值的方式来体现
library ieee;
use ieee.std_logic_1164.all;

entity threevoter is 
port (
    one : in std_logic;
    two : in std_logic;
    three : in std_logic;
    ispass : out std_logic
);
end threevoter;

architecture dataflow of threevoter is
    signal tempone, temptwo, tempthree, tempfour : std_logic;
    begin
        tempone <= one and two and ( not three );
        temptwo <= one and ( not two ) and three;
        tempthree <= ( not one ) and two and three;
        tempfour <= one and two and three;
        ispass <= tempone or temptwo or tempthree or tempfour;
end dataflow;

 

二

--*************第二种方式*******************
--行为描述方式，主要应用于数据流方式描述不太方便或是逻辑功能相对复杂的VHDL程序设计中，行为描述主要以进程语句来实现

library ieee;
use ieee.std_logic_1164.all;

entity threevoter2 is 
port (
    one : in std_logic;
    two : in std_logic;
    three : in std_logic;
    ispass : out std_logic
);
end threevoter2;

architecture dataflow of threevoter2 is
    signal temp : std_logic_vector ( 2 downto 0 );
    begin
        temp <= one & two & three;
        process ( temp )
            begin
                case temp is
                    when "110" =>
                        ispass <= '1';
                    when "101" =>
                        ispass <= '1';
                    when "011" =>
                        ispass <= '1';
                    when "111" =>
                        ispass <= '1';
                    when others =>
                        ispass <= '0';
                end case;
        end process;
end dataflow;

 

三

library ieee;
use ieee.std_logic_1164.all;

entity two_of_three is 
port (
    one : in std_logic;
    two : in std_logic;
    three : in std_logic;
    vote_out : out std_logic
);
end two_of_three;

architecture dataflow of two_of_three is
    begin
        vote_out <= one and two and ( not three );
end dataflow;

 

--*************第三种方式*******************
--结构化描述方式,主要应用于自顶向下的模块化设计,结构化描述方式一般是根据设计的逻辑功能进行模块划分，首先进行各个模块的设计
--与验证，最后在顶层文件里对多个模块进行调用
library ieee;
use ieee.std_logic_1164.all;

entity threevoter3 is 
port (
    one : in std_logic;
    two : in std_logic;
    three : in std_logic;
    ispass : out std_logic
);
end threevoter3;

architecture constrct of threevoter3 is
    component two_of_three
    port (
            one : in std_logic;
            two : in std_logic;
            three : in std_logic;
            vote_out : out std_logic
    );
    end component;
    
    signal tempone, temptwo, tempthree, tempfour : std_logic;
    begin
    
        instone : two_of_three
        port map 
        (
            one => one,
            two => two,
            three => three,
            vote_out => tempone
        );
        
        insttwo : two_of_three
        port map 
        (
            one => one,
            two => two,
            three => three,
            vote_out => temptwo
        );
        
        instthree : two_of_three
        port map 
        (
            one => one,
            two => two,
            three => three,
            vote_out => tempthree
        );
        
        instfour : two_of_three
        port map 
        (
            one => one,
            two => two,
            three => three,
            vote_out => tempfour
        );
        
        ispass <= tempone or temptwo or tempthree or tempfour;
        
        end constrct;

第三种方式的RTL: