eric.z

摘要：SystemVerilog Based Verification Methodology IntroductionVerification ChallengeVerification Techniques in VMM for SystemVerilogConstrained-random Stimulus GenerationCovera... 阅读全文

摘要：Code Coverage What is Code Coverage? Code coverage measurement simply determines those statements in a body of code have been executed through a test run and those which have not. In general, a code c... 阅读全文

摘要：One of the most interesting architectural decision in the design project is how to calculate the depth of a FIFO. FIFO is an intermediate logic where the data would be buffered or stored . Smaller FIF... 阅读全文

摘要：Here are some of the FAQs related to Static Timing Analysis. Please refer my previous topic for more information about STA.What is STA?STA stands for Static Timing Analysis, which is used to check whe... 阅读全文

摘要：. 任意字符？0或者1个* 任意个+ 一个或者以上$_ 默认数组$@ 第一被匹配的字符$` 被匹配字符之前的字符$' 被匹配字符之后的字符$1 第一个被匹配的字符，以左括号的顺序算。砖石输入符=~ 匹配判断符号\d 数字\D 非数字\w [A-Za-z0-9_]\W 非 [A-Za-z0-9_] \s 字符\S 非字符{n} 重复n次open FILE, "file.txt" 打开已经存在的文件open FILE,"file.txt" 打开file.txt,如果不存在的话就创建file.txtopen FILE,"file.txt" 打开，并将新内容追加到文本的末端，如果不存在的话， 阅读全文

摘要：倍频电路如下： 时钟切换电路，利用d锁存器原理： 时钟切换： 阅读全文

摘要：FPGA设计中常见的复位方式即同步复位和异步复位。在深入探讨亚稳态这个概念之前，特权同学也并没有对所谓的同步复位和异步复位有太多的注意，而在实践中充分感受了亚稳态的危害之后，回过头来细细品味《Verilog HDL设计与验证》一书中关于复位的章节，可谓受益匪浅。 在特权同学以前的代码里大多使用的是异步复位。 一个简单的异步复位的例子 always @ (posedge clk or neged... 阅读全文

摘要：Following is an example of a way to perform glitch-free clock gating. The clock is stalled in the high state one clock cycle after gate is asserted high. It is safe as long as the delay through the re... 阅读全文