2013年1月11日
verilog 和systemverilog的Timing Check Tasks
摘要： Formal Definition Timing Check Tasks are for verification of timing properties of designs and for reporting timing violations. Complete description: L 阅读全文
posted @ 2013-01-11 13:28 宙斯黄 阅读(2388) 评论(0) 推荐(0)