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Metris: bay area, san diego, texas

[apple]CAD Engineer – Timing for Transistor-Level Flows & Methodologies

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this role you will own defining, implementing, and supporting the methodologies, flows, and tools necessary to verify transistor-level circuits in the areas of timing, signal integrity and circuit verification. You will work very closely with digital and analog designers to ensure that their designs meet functionality, timing, electrical, power, and signal integrity goals. Key Qualifications • Typically requires at least 3+ years of hands on experience in timing, STA, CAD/methodology, etc. • Proficiency in STA and relevant methodologies for timing closure, signal integrity analysis, cross-talk, and OCV (AOCV, POCV) effects. • Proficiency in formal/functional/logic-to-circuit equivalence checking (FEC) techniques and implementation a plus. • Experience with transistor-level tools such as NanoTime, PathMill, ESP (Verilog to Spice equivalence checking), LEC, or HSPICE. • Familiarity with digital custom circuit designs including dynamic circuit techniques and memories as well as SPICE models and netlists. • Experience programming in Perl, TCL, or similar language. • Strong communicator who can accurately describe issues and follow them through to completion. Description In this exciting role, you will: • Collaborate with design teams to understand and debug tool issues and constraints • Build/maintain flows, scripts and methodologies for transistor level analysis • Work closely with both the Design and CAD teams to drive timing, power, signal integrity, and functional verification closure efforts • Perform deep analysis of timing paths to identify key issues • Document and help build guidelines/specs Education & Experience BS, MS preferred, degree in technical field

[apple]CAD Engineer - DFT

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices. In this hands-on role, you will utilize your experience in CAD to support DFT flows. You will write and support software and scripts that teams use to insert BIST/BIRA into designs, verify those systems, and manage test patterns. Key Qualifications Key Qualifications • 5+ years experience in relevant field preferred but not required. • Expertise in RTL simulators is desired • Expertise in linting, clock domain crossing, and power domain checking tools is desired. • You should have experience scripting in PERL and TCL • Good communication skills, previous customer support is a key. • Expertise in Design Compiler is desired • Expertise in Formality and/or Conformal is desired • Expertise in UPF is desired • Experience with infrastructure and CI/CD automation tools is a plus • Knowledge of ATE bringup process and test program management is desired Description Description You will be responsible for: Developing and maintaining an existing system for BIST insertion and DFT structure verification. Developing and maintaining existing automation and infrastructure for Product/Test Engineering and Silicon Validation teams. Working together with other CAD engineers to integrate your solutions in other flows. Utilizing your debugging experience to debug vendor tool problems and interacting with designers to help tackle their problems. Education & Experience Education & Experience MS/BS Degree in technical field Additional Requirements Additional Requirements

[apple]Synthesis - CAD Engineer

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. This is a highly visible role on a Front-End CAD and Methodology team, responsible for Synthesis and Formal Equivalence flows. This role will have a critical impact on getting functional products to hundreds of millions of customers quickly. Key Qualifications Key Qualifications • 3+ years of experience in relevant field • Experience scripting in TCL, Perl, or Python • Basic understanding of digital design and VLSI concepts is required • Exposure to Machine Learning techniques strongly preferred • Experience in Synthesis and Formal equivalence tools such as Design Compiler, RTL Compiler, Conformal LEC and/or Formality is required • Experience in linting, static timing analysis, power domain checking or place and route tools is a plus • Must have strong communication skills.

 

 

[google] Physical Design and Implementation Engineer, ASIC Hillside, NJ

Due to the current health crisis related to COVID-19 and the escalating visa/travel restrictions in place, we're currently unable to extend offers to anyone who cannot work from Bengaluru due to lockdown visa/travel restrictions, or other restrictive measures until further notice. Consequently, we will be prioritizing candidates who can start in this location by set date as expected. We're keeping the situation under review and would adjust our position should the restrictive measures be removed later on. Minimum qualifications: • Bachelor's degree in Electrical Engineering or equivalent practical experience. • 2 years of experience. • Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC). • Experience in high performance synthesis, PnR and sign-off optimizations. Experience in sign-off convergence, including STA, electrical checks and physical verification. Preferred qualifications: • Experience in computer architecture. • Knowledge of Verilog/SystemVerilog. • Understanding of circuit design, device physics and deep submicron technology. • Effective skills with scripting languages such as Python, Tcl, and/or Perl. About the job Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users. As a Physical Design and Implementation Engineer, you will develop high performance hardware and software to enable Google’s continuous innovations in working with Application Specific Integrated Circuits (ASIC). You will work with Architects and Logic Designers to drive architectural feasibility studies, develop timing and area design goals and exploring RTL/design tradeoffs for physical design closure. You'll also work with Verification and Software teams to understand and implement the design requirements for clocking management. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities • Develop all aspects of ASIC RTL2GDS implementation for high PPA designs. • Manage block and full-chip level physical implementation and QoR (timing, area).

 

[google] Physical Design Engineer, Static Timing Analysis >>> it seems hard

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users. As a Physical Design Engineer on the chip implementation team, you will work on the physical implementation of ASICs using advanced technology nodes. You will develop physical design methodologies, automation scripts, and write documentation. You will perform technical evaluations of vendors, process nodes, and IP and will provide recommendations. Additionally, you will work with architecture, logic design, and design for testing teams to understand and implement their requirements

[AMD] Mixed-Signal Timing Analysis engineer- 81240

Title : Mixed signal timing analysis engineer

The Role : The candidate will be a member of the SerDes mixed-signal design team responsible for timing characterization and some implementation of high-speed digital blocks within the mixed-signal portion of the design

The Person : Strong communication and interpersonal skills.

Responsibilities

• Internal/external timing characterization of state-of-the-art, high-speed (32+ GS/s), mixed-signal blocks
• Working closely with the mixed-signal, physical design, and layout teams to drive timing closure and efficient, robust implementations
• Delivering high-quality external timing characterization to the physical and logical design teams

Preferred Skill Sets

• Experience in transistor- and gate-level static timing and noise analysis.
• Experience in transistor- and gate-level custom logic design, particularly high-speed timing paths.
• Experience in timing / SDC constraints generation and management.
• Experience in RTL design is a plus.
• Experience with NanoTime or PrimeTime tools.
• Good understanding of tool algorithms for noise glitch, cross-talk delay, and margining with OCV / POCV.
• Proficiency in circuit modeling and simulation, including SPICE models and worst-case corner selection.
• Proficiency in scripting languages (Perl, python).
• Strong communication and interpersonal skills.

Education : Masters/Bachelors/PhD in Electrical/Electronics Engineering

 

Conclusion: from the jobs I want to do, it seems there is no connection with the pure software, I should focus on what cadence job can bring me and what I learn from this period, and learn about points, finally point is the leetcode.