永不止步，永无止境

摘要： Hi all, Xilinx recommend using SRL16 to make large delay instead of cascade flip-flops. Can you tell me the advantages of it? And for the large delay, it often uses SRL16+flip-flop which means the last delay element is flip-flop. Can you tell me why the last delay element is not SRL16 but a flip-flo 阅读全文