yanhc

摘要： module tb_DFF ( clk, d, q ); input clk; input d; output q; reg q; always @ (posedge clk) q <= d; endmodule 测试文件： `timescale 1ns / 1psmodule ttbb_DFF; // Inputs reg clk; reg d; // Outputs wire q; // Instantiate the Unit Under Test (UUT) tb_DFF uut ( .clk(clk), .d(d), .q(q) ); initial beg... 阅读全文