# Verilog整理

1.两种实例化

2.运算符//逻辑运算+按位运算//拼接运算符

3.reg默认为1位

4.{16{1}}与{16{1'b1}}不同

5.[1023:0] in

ha[3:0]=(in>>(4*sel))

6.三位全加器

 1  module add(
2
3                 input a, b, cin,
4
5                 output cout, sum
6
7         );
8  assign cout=a&b|a&cin|b&cin,sum=a^b^cin;
9  endmodule
10  module top_module(
11
12                 input [2:0] a, b,
13
14                 input cin,
15
16                 output [2:0] cout,
17
18                 output [2:0] sum );
22 endmodule

7. 区别reg a[7:0]与reg [7:0]a.

8.区分output reg out=0与output reg out

9.always不能嵌套

10.检测上升沿下降沿的小算法

module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0] e,pd;
assign anyedge=pd;
integer i;
always  @(posedge clk)begin
for(i=0;i<8;i=i+1)
e[i]<=in[i];
end
always @(posedge clk)begin
for(i=0;i<8;i=i+1)
if(!e[i]&&in[i])
pd[i]<=1;
else pd[i]=0;
end
always @(posedge clk)begin
for(i=0;i<8;i=i+1)
if(e[i]&&!in[i])
pd[i]<=1;
else pd[i]=0;
end
endmodule

posted @ 2019-11-13 09:34  xxmlala  阅读(27)  评论(0编辑  收藏