摘要: 1 //testbench 2 `timescale 1ns/1ns 3 module lcd_spi_m_tb(); 4 reg rst_n_i; 5 reg spi_clkx_i; 6 reg [31:0] spi_data_i; 7 reg spi_start; 8 reg spi_miso_ 阅读全文
posted @ 2023-11-29 19:09 xgj_0817 阅读(93) 评论(0) 推荐(0)