SystemVerilog-断言

常用断言

assert property (@(posedge clk) disable iff(~rstn) (a -> b));
assert property (@(posedge clk) disable iff(~rstn) (a === b));	
assert property (@(posedge clk) disable iff(~rstn) (onehot0(grant));

property assert_pc_must_hw_aligned;
   @(posedge clk) disable iff(~rstn) 
      ~pcgen_fetch_pc_o[0];
endproperty
assert property(assert_pc_must_hw_aligned) else $error(“%m”: fetch pc is not half_word_aligned, please check!!!”);

参考

systemverilog学习（9）assertion
断言语法总结