wkl7123

摘要： 1 module main(); 2 reg clk=0; 3 reg [11:0] a=0; 4 reg [11:0] b=0; 5 always #50 clk=~clk; 6 always@(clk) 7 begin 8 a=a+4; 9 b<=a/4;10 end11 endm... 阅读全文

摘要： 1 module main(); 2 reg [5:0] a=0; 3 reg [5:0] b=0; 4 reg clk=0; 5 6 always@(clk) 7 begin 8 a<=a+3; 9 b<=b+1;10 end11 12 always@(b)13 begin14 ... 阅读全文