1 module cnt_test(
2 clk,
3 rst_n,
4 en1,
5 // en2,
6 // en3,
7 dout
8 );
9
10 input clk;
11 input rst_n;
12 input en1;
13 //input en2;
14 //input en3;
15
16 output [2:0] dout;
17
18 reg [2:0] dout;
19 reg flag_add;
20
21 reg [3:0] cnt0;
22 reg [3:0] cnt1;
23 reg [3:0] x;
24 reg [3:0] y;
25 //reg [3:0] z;
26 //reg [3:0] flag_sel;
27
28 wire add_cnt0;
29 wire end_cnt0;
30
31 wire add_cnt1;
32 wire end_cnt1;
33
34 always @(posedge clk or negedge rst_n)begin
35 if(!rst_n)begin
36 cnt0 <= 0;
37 end
38 else if(add_cnt0)begin
39 if(end_cnt0)begin
40 cnt0 <= 0;
41 end
42 else begin
43 cnt0 <= cnt0 + 1;
44 end
45 end
46 end
47
48 assign add_cnt0 = flag_add;
49 assign end_cnt0 = add_cnt0 && cnt0 == x - 1;
50
51 always @(posedge clk or negedge rst_n)begin
52 if(!rst_n)begin
53 cnt1 <= 0;
54 end
55 else if(add_cnt1)begin
56 if(end_cnt1)begin
57 cnt1 <= 0;
58 end
59 else begin
60 cnt1 <= cnt1 + 1;
61 end
62 end
63 end
64
65 assign add_cnt1 = end_cnt0;
66 assign end_cnt1 = add_cnt1 && cnt1 == 3 - 1;
67
68 always @(posedge clk or negedge rst_n)begin
69 if(!rst_n)begin
70 flag_add <= 0;
71 end
72 else if(en1)begin
73 flag_add <= 1;
74 end
75 else if(end_cnt1)begin
76 flag_add <= 0;
77 end
78 end
79
80 always @(posedge clk or negedge rst_n)begin
81 if(!rst_n)begin
82 dout <= 0;
83 end
84 else if(add_cnt0 && cnt0 == 1-1)begin
85 dout <= y;
86 end
87 else if(end_cnt0)begin
88 dout <= 0;
89 end
90 end
91
92 always @(*)begin
93 if(cnt1 == 0)begin
94 x = 4;
95 y = 3;
96 end
97 else if(cnt1 == 1)begin
98 x = 3;
99 y = 2;
100 end
101 else begin //省去if(cnt1 == 2)
102 x = 2;
103 y = 1;
104 end
105 end
106
107 endmodule
