CSC3050 Project 3: RISC-V Simulator
CSC3050 Project 3: RISC-V Simulator
1 Background Efficient execution of instructions in a RISC-V pipeline relies on avoiding data hazards, where an instructiondepends on the result of a previous instruction reducing the efficiency of the processor. To mitigate these hazards, instruction reordering and specialized fused
operations like fmadd (fused multiply-add) can be utilized.This assignment has two parts:
- Implementing the fmadd Instruction In this part, you will implement the fused multiply-add (fmadd)
instruction, which performs a multiplication followed by an addition in a single step. This reduces
the number of instructions executed and can eliminate certain data hazards, leading to more efficient
computation.
- Reordering Instructions to Avoid Data Hazards You will be given a sequence of RISC-V instructions (add/mul) that suffer from data hazards. Your task will be to rearrange them while maintaining
correctness. This exercise will help you understand the importance of instruction scheduling in hazardmitigation and performance optimization.By completing this assignment, you will gain some basic hands-on experience with hazard avoidance
sow instruction reordering can improve pipeline execution efficiency.
2 RISC-V GNU Toolchain
RISC-V GNU Toolchain is already in your Docker, so you do not need to download it from the official link.
ut we highly suggest that you open the official link and read the README.
his toolchain supports the RISC-V 32I instruction set with M extension (integer multiplication and division),based on the RISC-V Specification 2.2. Follow these steps to configure and compile the toolchain:reate a build directory, configure the toolchain, and compile it with the following commands:mkdir build; cd build../configure --with-arch=rv32im --enable-multilib --prefix=/path/to/riscv32imake -j$(nproc)3 A Simple RISC-V64I Simulator
We use a modified version of Hao He‘s simulator. You can find the modified repository:1https://github.com/EnderturtleOrz/CSC3050-2025-Spring-Project-3.It is a simple RISC-V Emulator suppprting user mode RV64I instruction set, from PKU Computer Architecture
Labs, Spring 2019.
3.1 Compile
mkdir build
cd build
cmake ..
make
3.2 Usage ./Simulator riscv-elf-file-name [-v] [-s] [-d] [-b strategy]
3.3 Parameters
- -v for verbose output, can redirect output to file for further analysis.
- -s for single step execution, often used in combination with -v.
- -d for creating memory and register history dump in dump.txt.
- -b for branch prediction strategy (default BTFNT), accepted parameters are AT, NT, BTFNT, and BPB.
– AT: Always Taken
– NT: Always Not Taken– BTFNT: Back Taken Forward Not Taken
– BPB: Branch Prediction Buffer (2-bit history information)
4 Part I: RISC-V32I Simulator
The first task in this assignment is to change the RISC-V64I simulator to be RISC-V32I simulator. This is an
easy job, but we suggest that you carefully read the code and know the logical structure of the simulator.
You can re-compile the sample test cases to test your RISC-V32I simulator. Take quicksort as an example:
riscv32-unknown-elf-gcc -march=rv32i \
test/quicksort.c test/lib.c -o riscv-elf/quicksort.riscv
You can change -march=rv32i to -march=rv32imf for the remain part of the assignment.
5 Part I: Fused Instructions
The fused instruction is part of the RISC-V ISA’s F (single-precision floating-point) and D (double-precisionfloating-point) extensions. These extensionsprovide support for floating-point arithmetic operations. In thisproject, you only need to implement the integer version.
2Take fmadd.s instruction as an example.This代写 CSC3050 Project 3: RISC-V Simulator instruction performs a fused multiply-add operation for floating-point numbers, which means it computesthe product of two floating-point numbers and then adds a third floating-point number to the result, all in asingle instruction. Obviously, this operation is beneficial for both performance and precision, as it reduces the
number of rounding errors compared to performing the multiplication and addition separately.In this assignment, you are required to implement the fusedinstruction for integer type. We used the sameformat as the standard RISCV R4 instruction. We used the reserved custom opcode 0x0B as our opcode.
5.1 R4 Instruction
R4 instructions, as in Figure 1, involve four registers (rs1, rs2, rs3, rd), which is different from those you are
familiar with. To use standard R4 format, you need to add F-extension when compiling. In other words you
should use -march=rv32if but NOT change the compiling commands of RISC-V GNU Toolchain. (Again,
we are not using floating-points.)
Figure 1: R4 format
5.2 Cycle counts
The fused instruction needs more cycles to process, so we define that our fused instruction needs 3 more
ycles to execute. Specifically, the number of cycles required to complete this instruction is +3 compared totandard instructions. The mul instruction alsoincurs an additional 3 cycles, making fmadd more efficient ierms of cycle count.
Suppose add instruction takes 5 cycles to complete, then we have:
add(1) + mul(3) = 4 > fmadd(3)
5.3 Other Important Information
We also provide some basic test cases for reference. Please refer to the README and /test-fused underthe root of the project.Also, you can try to compare the number of cycles between fused instructions and basic mul and add instructions.
36 Part I: Disable Data Forwarding
Add an option -x to disable data forwarding.
You can modify the logical of parsing arguments in the method parseParmeters in MainCache.cpp.
7 Part II: Introduction
In this part of the assignment, you will analyze a given sequence of RISC-V instructions that suffer from dathazards. (With forwarding turned off) Your task is to rearrange these instructions while maintaining correctness, ensuring that the processor pipeline executes efficiently. Then, you should be able to further optimize itby substituting add/mul operations with fmadd operations. By strategically reordering instructions, you will
learn how to reduce stalls, improve instruction throughput, and optimize execution flow in a pipelined RISC-Varchitecture.
8 Part II: Rearrange
In the part2.s file, you will find a RISC-V program that contains several data hazards affecting pipelineefficiency. Your task is to rearrange the instructions tominimize stalls while ensuring the program producesthe same output as the original. You should startby reviewing and running part2.s in the simulator tounderstand its functionality and identify potential improvements. Your optimized version should preservecorrectness while reducing the number of stalled cycles. Grading will be based on both correctness and
execution efficiency (fewer cycles due to reduced hazards). Name your result with part2 p2.s 9 Part II: Using fmadd.i
After optimizing part2.s, you may identify opportunities to replace certain instruction sequences with the moreefficient fmadd.i instruction (based on eitherpart2.s or part2 p2.s). The final optimized file, part2 p3.s,
should produce the same output as both part2.s and part2 p2.s while improving execution efficiency. Sincefmadd.i combines multiplication and addition into a single operation, the total cycle count should be furtherreduced. Grading will be based on both correctness and execution efficiency. Name your optimized filepart2 p3.s before submission.
10 Grading Criteria
The maximum score you can get for this lab is 100 points, and it is composed by the following components:
- Part 1 correctness of implementation 55 pts
- Part 2 correctness of part2 p2.s 20 pts
- Part 2 efficiency of part2 p2.s 20 pts
- A short report about anything you have learn in this project 5 pts
- Part 2 correctness of part2 p3.s Extra Credit 1 pts
- Part 2 efficiency of part2 p3.s Extra Credit 1 pts
411 Submission
You should make sure your code compiles and runs. Then, it should be compressed into a .zip file andsubmitted to BlackBoard. Any necessary instructions to compile and run your code should also be documented and included. Finally, you are also required to include a report containing the results of your testcase execution.
