section 1
摘要:1. quartus setup 1.1 assignment-->setting 1.2 editor-> sdc file case sensitive2. core timing 2.1 create_clock 2.2 derive_pll_clockcreate_generated_clocktransceiver_clock 2.3 derive_clock_uncertainty 2.4 set_clock_groupsun-relatedoptions -asynchronous,-exclusive ASIC, no matters in FPG...
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posted @ 2013-04-07 11:18
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