摘要： 一、Reset_Delaymodule Reset_Delay(iCLK,oRESET);input iCLK;output reg oRESET;reg[19:0] Cont;always@(posedge iCLK) begin if(Cont!=20'hfffff) begin Cont<=Cont+1; oRESET<=1'b0; end else oRESET<=1'b1; endendmodule二、video_sync_generatormodule video_sync_generator(input rst_n,input vga_c 阅读全文