摘要： module LFSR ( input clk, input rst_n, output out);reg [9:0] q=10'b1010101010;wire tap = q[2]^q[9];assign out = q[9];always @ (posedge clk,negedge rst_n)if(!rst_n) q <= 10'b1010101010;else q <= {q[8:0],tap};endmodule将LFSR赋初始值1010101010，最低为q0=q2 xor q9,输出为最高位q9;测试程序如下：`timescale 1 ns/1 n 阅读全文