CORDIC算法--流水线结构
摘要：
cordic算法的Verilog实现module cordic#(parameter DATA_WIDTH=8)( input clk, input rst_n, input ena, input [DATA_WIDTH-1:0] phase_in, output reg [DATA_WIDTH-1:0] sin_out, output reg [DATA_WIDTH-1:0] cos_out, output reg [DATA_WIDTH-1:0] eps);localparam PIPELINE=8;reg [DATA_WIDTH-1:0] phase_in_reg;reg [DATA_W 阅读全文
posted @ 2010-07-28 14:51 齐威王 阅读(8970) 评论(10) 推荐(4) 编辑