02 2020 档案

Verilog 2001 `default_nettype none
摘要：在Verilog 1995規定，對於沒宣告的信號會自動視為wire，這樣常常造成debug的困難，Verilog 2001另外定義了`default_nettype none，將不再自動產生wire. 1 module default_nettype_none (2 input n0,3 input 阅读全文
posted @ 2020-02-13 10:03 pttkvin 阅读(2819) 评论(0) 推荐(0)
[Perl] Parsing the sheet of excel file to verilog file
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posted @ 2020-02-05 22:04 pttkvin 阅读(1) 评论(0) 推荐(0)
[Verilog] indexed part-select +:
摘要：That syntax is called an indexed part-select. The first term is the bit offset and the second term is the width. It allows you to specify a variable f 阅读全文
posted @ 2020-02-05 21:50 pttkvin 阅读(648) 评论(0) 推荐(0)