hdlbits.01xz.net答案/circuits/combinational logic/multiplexer

1.Mux2to1

module top_module( 
    input a, b, sel,
    output out ); 
    assign out = (sel)? b : a;
endmodule

2.Mux2to1V

module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );
    assign out = (sel) ? b : a;
endmodule

3.Mux9to1v

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
	
    always@(a or b or c or d or e or f or g or h or i or sel)
        begin
            case(sel)
                4'd0: out = a;
                4'd1: out = b;
                4'd2: out = c;
                4'd3: out = d;
                4'd4: out = e;
                4'd5: out = f;
                4'd6: out = g;
                4'd7: out = h;
                4'd8: out = i;
                default: out = 16'hffff;
            endcase
        end         
endmodule

4.mux256to1

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );
    assign out = in[sel];
endmodule

5.Mux256to1v
这一题要强调一个语法知识：
这样的一个错误"... is not a constant"意味着被选择的位宽不是常数，因此in[ sel4+3 : sel4 ]就会报错。
通常在Verilog当中in[var],var可以是变量，但是不允许 in [var1 : var2]两个都是变量。

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
    assign out[0] = in[4*sel];
    assign out[1] = in[4*sel + 8'd1];
    assign out[2] = in[4*sel + 8'd2];
    assign out[3] = in[4*sel + 8'd3];
endmodule

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[习题链接]（https://hdlbits.01xz.net/wiki/Mux2to1）