hdlbits.01xz.net答案/circuits/combinational logic/basic

1.wire

module top_module (
input in,
output out);

assign out = in;
endmodule

2.GND

module top_module (
output out);
assign out = 1'b0;
endmodule

3.NOR

module top_module (
input in1,
input in2,
output out);
assign out = ~(in1|in2);

endmodule

4.Another gate

module top_module (
input in1,
input in2,
output out);
assign out = in1 & (~in2);
endmodule

5.Two gates

module top_module (
input in1,
input in2,
input in3,
output out);
assign out = in3 ^ (~(in1 ^ in2));
endmodule

6.Gates

module top_module(
input a, b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a&b;
assign out_or = a|b;
assign out_xor = a^b;
assign out_nand = ~(a&b);
assign out_nor = ~(a|b);
assign out_xnor = ~(a^b);
assign out_anotb = a&(~b);

endmodule

7.7420

module top_module (
input p1a, p1b, p1c, p1d,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );

assign p1y = ~(p1a & p1b & p1c & p1d);
assign p2y = ~(p2a & p2b & p2c & p2d);
endmodule

8.TruthTable

这里我稍作化简了。

module top_module(
input x3,
input x2,
input x1, // three inputs
output f // one output
);
assign f = ((~x3) & x2) | (x3 & x1);
endmodule

9.Two-bit equality

module top_module ( input [1:0] A, input [1:0] B, output z );
always@(A or B)
begin
if(A == B)
z = 1;
else
z = 0;
end
endmodule

10.simple circuitA

module top_module (input x, input y, output z);
assign z = (x^y)&x;
endmodule

11.simple circuit B

module top_module ( input x, input y, output z );
assign z = ~(x^y);
endmodule

12.Combination Circuit A and B

module top_module (input x, input y, output z);
wire temp1;
wire temp2;
wire temp3;
wire temp4;

A IA1(x,y,temp1);
B IB1(x,y,temp2);
A IA2(x,y,temp3);
B IB2(x,y,temp4);

assign z = (temp1 | temp2) ^ (temp3 & temp4);

endmodule

module A(input a, input b, output c);
assign c = (a^b)&a;
endmodule

module B(input a, input b, output c);
assign c = ~(a^b);
endmodule

13.ringer

module top_module (
input ring,
input vibrate_mode,
output ringer, // Make sound
output motor // Vibrate
);

assign motor = (vibrate_mode & ring) ? 1'b1 : 1'b0;//如果不写位数会警告
assign ringer = ((~vibrate_mode) & ring)? 1'b1:1'b0;
endmodule

14.Thermastat

module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater = (mode & too_cold)? 1'b1 : 1'b0;
assign aircon = ((~mode) & too_hot)?1'b1 : 1'b0;
assign fan = (((mode & too_cold) | ((~mode) & too_hot))| fan_on)? 1'b1 : 1'b0;

endmodule

15.popconut3

module top_module(
input [2:0] in,
output [1:0] out );

reg[1:0] count;
integer i;
always@(in)
begin
count = 2'b0;
for(i = 0; i < 3; i++)
begin
if(in[i]==1)
count = count + 2'b1;
end
out = count;
end
endmodule

16.Gates and Vectors

module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );

integer i;
always@(in)
begin
for(i = 0; i < 3; i++)begin
out_both[i] = in[i] & in[i+1];
out_any[i+1] = in[i] | in[i+1];
out_different[i] = in[i] ^ in[i+1];//当然编程可以考虑用模运算但是硬件实现显然不推荐。
end
out_different[3] = in[3]^in[0];
end

endmodule

17.GatesV100

module top_module(
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different );

integer i;
always@(in)
begin
for(i = 0;i < 99; i++)
begin
out_both[i] = in[i] & in[i+1];
out_any[i+1] = in[i] | in[i+1];
out_different[i] = in[i] ^ in[i+1];
end
out_different[99] = in[99] ^ in[0];
end

endmodule

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代码如有错误还请指正。

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