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从adder2开始更新
1.adder2
本题中题目已经写好adder16,切勿再写

module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);//top module contains two 16bit adder.
    wire cout1;
        add16 add16_lo(a[15:0],b[15:0],0,sum[15:0],cout1);
        add16 add16_hi(a[31:16],b[31:16],cout1,sum[31:16],);//高16位的进位舍去

endmodule

module add1 ( input a, input b, input cin,  output sum, output cout );
// Full adder module here
    assign sum = a^b^cin;
    assign cout = (a&b)|(a&cin)|(b&cin);
endmodule

2.Module cseladd
本题就体现了电路设计中面积换时间的思想。

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire cout1;
    wire[15:0] tempOut0;
    wire[15:0] tempOut1;
    add16 add_1(a[15:0],b[15:0],0,sum[15:0],cout1);
    add16 add_2(a[31:16],b[31:16],0,tempOut0[15:0],);
    add16 add_3(a[31:16],b[31:16],1,tempOut1[15:0],);
    assign sum[31:16] = cout1? tempOut1 : tempOut0;
endmodule

Module addsub

module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);
    wire cout1;
    wire[31:0] bSub;
    assign bSub = ~b + 1;
    wire[31:0] realb;
    
    assign realb = sub? bSub : b;
    add16 add_1(a[15:0],realb[15:0],0,sum[15:0],cout1);
    add16 add_2(a[31:16],realb[31:16],cout1,sum[31:16],);

endmodule

4.Alwaysblock1

module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);
    assign out_assign = a & b;
    always@( a or b)
        out_alwaysblock = a & b;

endmodule