摘要：
6 generate statemachine 1 -- port 2 cmd_ack : out std_logic; -- command completed 3 4 -- architecture 5 type states is (idle, start_a,... 阅读全文
posted @ 2015-05-07 10:09
mengdie
阅读(215)
评论(0)
推荐(0)
摘要：
4) detect start/stop condition START- falling edge on SDA while SCL is high; STOP -rising edge on SDA while SCL is high 1 -- block 2 signal st... 阅读全文
posted @ 2015-05-07 09:53
mengdie
阅读(298)
评论(0)
推荐(0)
摘要：
FPGA proven, AISC proven, I2C controllercore from OpenCoreshttp://opencores.org/project,i2cBit-controller5 block 1) capture SCL and SDA 1 -- por... 阅读全文
posted @ 2015-05-07 08:25
mengdie
阅读(408)
评论(0)
推荐(0)
摘要：
4 generate clock and control signals 1 -- architecture 2 signal iscl_oen, isda_oen : std_logic; -- internal I2C lines 3 signal sda_chk ... 阅读全文
posted @ 2015-05-07 08:00
mengdie
阅读(368)
评论(0)
推荐(0)
摘要：
FPGA proven, AISC proven,I2C controllercorefrom OpenCoreshttp://opencores.org/project,i2cBit-controller-- Translate simple commands into SCL/SDA trans... 阅读全文
posted @ 2015-05-07 07:28
mengdie
阅读(707)
评论(0)
推荐(0)
浙公网安备 33010602011771号