随笔档案「2015年7月」 - mengdie

Tcl之Read files for synthesis

摘要：The following file is to read all design files into syntehsis tool automatically, like Cadence RTL Compiler. 1 set srcbasic ${HDLPATH}/01_V... 阅读全文

posted @ 2015-07-28 20:15 mengdie 阅读(571) 评论(0) 推荐(0)

Verilog之event

摘要：1 Explicit event The value changes on nets and variable can be used as events to trigger theexecution of a statement. The event can also be based o... 阅读全文

posted @ 2015-07-28 19:31 mengdie 阅读(978) 评论(0) 推荐(0)

Tcl之Math

摘要：expr is for Tcl to do math operations. Ittakes all of its arguments ("2 + 2" for example) and evaluates the result as a Tcl "expression". Many comma... 阅读全文

posted @ 2015-07-28 17:43 mengdie 阅读(369) 评论(0) 推荐(0)

Digital design之Boolean Algebra

摘要：1.　0 and 1 (duality: 0 -- 1, ·-- +) X + 0 = X, X·1 = X X + 1 = 1, X ·0 = 02.　Idempotent X + X = X, X ·X = X3.　Involution (X')' = X4.　Complement... 阅读全文

posted @ 2015-07-27 22:31 mengdie 阅读(226) 评论(0) 推荐(0)

Assembly之instruction之Status register

摘要：The status register (SR/R2), used as a source or destination register, can beused in the register mode only addressed with word instructions. The re... 阅读全文

posted @ 2015-07-27 20:35 mengdie 阅读(221) 评论(0) 推荐(0)

Assembly之instruction之JC

摘要：JC Jump if carry setJHS Jump if higher or sameSyntax JC label JHS labelOperation If C = 1: PC + 2 × offset −> PC If C = 0: exec... 阅读全文

posted @ 2015-07-27 20:19 mengdie 阅读(370) 评论(0) 推荐(0)

STA之Concepts (2)

摘要：3 Skew between signals Skew is the difference in timing between two or more signals, maybe data,clock or both. Clock latency is the total time itta... 阅读全文

posted @ 2015-07-22 22:50 mengdie 阅读(655) 评论(0) 推荐(0)

STA之Concepts (1)

摘要：Static Timing Analysis is one of the many techniques available to verify the timing of a digital design. An alternate approach used to verify the ti... 阅读全文

posted @ 2015-07-21 21:19 mengdie 阅读(504) 评论(0) 推荐(0)

Shell script之How to write

摘要：Write shell script:　1) Editor like vi or mcedi　2) Set execute permission for your script chmod permission your-script-name$ chmod +x your-script... 阅读全文

posted @ 2015-07-10 19:25 mengdie 阅读(297) 评论(0) 推荐(0)

QS之shell script

摘要：1 Invoke Mdoelsim In order to open Modelsim automatically, it is better to use a shell script to invoke modelsim. 1 #!/bin/bash 2 # --------------... 阅读全文

posted @ 2015-07-10 19:12 mengdie 阅读(271) 评论(0) 推荐(0)

VHDL之Serial-Parallel Multiplier

摘要：1 Serial-parallel multiplier Figure 12.1 shows the RTL diagram of a serial-parallel multiplier. One of the inputvectors (a) is applied serially to t... 阅读全文

posted @ 2015-07-09 23:57 mengdie 阅读(857) 评论(0) 推荐(0)

Tcl之looping

摘要：1 While loopwhile test body Thewhilecommand evaluatestestas an expression. Iftestis true, the code inbodyis executed. After bodyhas been executed,... 阅读全文

posted @ 2015-07-06 23:18 mengdie 阅读(250) 评论(0) 推荐(0)

VHDL_ADC之cic_diffcell

摘要：1 library IEEE; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 library edclib; 6 use edclib.pkg_xxxlib.all; -- package from company... 阅读全文

posted @ 2015-07-06 22:06 mengdie 阅读(376) 评论(0) 推荐(0)

RTL Compiler之Example

摘要：Synthesis　=　Translation + Logic Optimization + Mapping Step 1 Source files　1)　make directory1 mkdir Lab2 cd Lab3 mkdir HDL4 cd H... 阅读全文

posted @ 2015-07-01 15:49 mengdie 阅读(1064) 评论(0) 推荐(0)