随笔分类 -  VHDL

摘要:源程序:注意红色字体为之后对比的中将做改动的语句 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity control is port(clk:in std_logic; dip1:in std_logic; -... 阅读全文
posted @ 2011-12-16 23:40 maliqian 阅读(5924) 评论(0) 推荐(0)