Wishbone总线接口RAM

 1 /*
 2 ************************************************************************************************
 3 *    File   : wb_ram.v
 4 *    Module : wb_ram
 5 *    Author : Lyu Yang
 6 *    Date   : 01,01,1970
 7 *    Description : wishbone generic ram
 8 ************************************************************************************************
 9 */
10 
11 // synthesis translate_off
12 `timescale 1ns / 10ps
13 // synthesis translate_on
14 module wb_ram (
15     input    wire                wb_clk_i,
16     input    wire                wb_rst_i,
17     input    wire                wb_cyc_i,
18     input    wire                wb_stb_i,
19     input    wire                wb_we_i,
20     input    wire    [3:0]        wb_sel_i,
21     input   wire    [31:0]        wb_adr_i,
22     input    wire    [31:0]        wb_dat_i,   
23     output    reg        [31:0]      wb_dat_o,
24     output    reg                 wb_ack_o
25 );
26 
27 parameter mem_words = 4096;
28 
29 wire [31:0]        wr_data;
30 
31 // mux for data to ram
32 assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
33 assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
34 assign wr_data[15: 8] = wb_sel_i[1] ? wb_dat_i[15: 8] : wb_dat_o[15: 8];
35 assign wr_data[ 7: 0] = wb_sel_i[0] ? wb_dat_i[ 7: 0] : wb_dat_o[ 7: 0];
36 
37 // genarate ack signal
38 always @ (posedge wb_clk_i)
39 begin
40     if(wb_ack_o)
41         wb_ack_o <= 1'b0;
42     else if(wb_cyc_i & wb_stb_i & !wb_ack_o)
43         wb_ack_o <= 1'b1;
44     else wb_ack_o <= 1'b0;
45 end
46 
47 // memory
48 reg [31: 0] ram [0 : mem_words - 1];
49 
50 initial $readmemh("../../data.txt", ram);
51 
52 always @ (posedge wb_clk_i)
53 begin 
54     wb_dat_o <= ram[wb_adr_i[31:2]];
55     if(wb_cyc_i & wb_stb_i & wb_we_i & wb_ack_o)
56         ram[wb_adr_i[31:2]] <= wr_data;
57 end 
58 
59 endmodule

 

posted @ 2016-12-06 09:04 绿杨 阅读(...) 评论(...) 编辑 收藏